Method to form self-aligned tips for flat panel displays
AssigneeMicron Technology, Inc.
InventorGurtej S. Sandhu
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Abstract
The present invention develops a process wherein a method for fabrication of field emission tips for flat panel displays and in particular to the formation of an array of self-aligned emission cathode tips. The method forms self-aligned ultra-sharp cathode tips out of a conducting material by etching contacts into an insulator which encloses a grid of conducting lines which will serve as the anodes. Next, a film having poor step coverage is deposited into the contacts followed by a selective deposition of a conducting material thereby resulting in a cone shaped configuration. Then the film is etched selective to the cone followed by the sharpening of the cone tip by conventional methods, thereby resulting in an array of evenly-spaced self-aligned emission cathodes having ultra-sharp tips.
Claims42
A process for forming conductive self-aligned emission cathode tips on a starting substrate for use in flat panel displays, said process comprising the steps of:
- a) forming a first dielectric layer superjacent and coextensive said starting substrate;
- b) placing and patterning a first conductive layer superjacent and coextensive said first dielectric layer, said patterning of said first conductive layer resulting in a conductive grid structure having a plurality of a first set of parallel conductive lines in intersection with a plurality of a second set of parallel conductive lines and a plurality of exposed portions of said first dielectric layer;
- c) forming a second dielectric layer superjacent and coextensive said conductive grid structure and exposed portions of said first dielectric layer;
- d) etching a buried contact opening at each grid intersection thereby exposing portions of said starting substrate, and forming patterned edges in each layer bordering each said contact opening;
- e) forming a sacrificial layer superjacent and coextensive said second dielectric layer and the patterned edges of said second dielectric layer, said first conductive layer and said first dielectric layer thereby forming cone-shaped voids at said exposed portions of said starting substrate;
- f) placing a second conductive layer into said cone-shaped voids thereby connecting to said exposed portions of said starting substrate;
- g) removing said sacrificial layer thereby forming said self-aligned cathode emission tips;
- and
- h) sharpening said emission tips.
A process for forming conductive self-aligned emission cathode tips on a starting substrate for use in flat panel displays, said process comprising the steps of:
- a) forming a first dielectric layer superjacent and coextensive said starting substrate;
- b) placing and patterning a first conductive layer, superjacent and coextensive said first dielectric layer, said patterning of said first conductive layer resulting in a conductive grid structure having a plurality of a first set of parallel conductive lines in intersection with a plurality of second set of parallel conductive lines and a plurality of exposed portions of said first dielectric layer;
- c) forming a second dielectric layer superjacent and coextensive said conductive grid structure and exposed portions of said first dielectric layer;
- d) etching a buried contact opening at each grid intersection thereby exposing portions of said starting substrate;
- e) forming a sacrificial layer superjacent and coextensive said second dielectric layer and the patterned edges of said second dielectric layer, said first conductive layer and said first dielectric layer thereby forming cone-shaped voids at said exposed portions of said starting substrate;
- f) placing a second conductive layer selectively into said cone-shaped voids thereby connecting to said exposed portions of said starting substrate;
- g) removing said sacrificial layer thereby forming said self-aligned cathode emission tips;
- and
- h) sharpening said emission tips
A process for forming conductive self-aligned emission cathode tips on a starting substrate for use in flat panel displays, said process comprising the steps of:
- a) forming a first dielectric layer superjacent and coextensive said starting substrate;
- b) placing and patterning a first conductive layer superjacent and coextensive said first dielectric layer, said patterning of said first conductive layer resulting in a conductive grid structure having a plurality of a first set of parallel conductive lines in intersection with a plurality of a second set of parallel conductive lines and a plurality of exposed portions of said first dielectric layer;
- c) forming a second dielectric layer superjacent and coextensive said conductive grid structure and exposed portions of said first dielectric layer
- d) etching a buried contact opening at each grid intersection thereby exposing portions of said starting substrate;
- e) forming a sacrificial layer superjacent and coextensive said second dielectric layer and the patterned edges of said second dielectric layer, said first conductive layer and said first dielectric layer thereby forming cone-shaped voids at said exposed portions of said starting substrate;
- f) placing blanketing second conductive layer superjacent said sacrificial layer and into said cone-shaped voids thereby connecting to said exposed portions of said starting substrate;
- g) isotropically etching said second conductive layer thereby exposing said sacrificial layer while leaving said second conductor residing inside said cone-shaped voids;
- h) removing said sacrificial layer thereby forming said self-aligned cathode emission tips;
- and
- i) sharpening said emission tips.
Dependencies are inferred from the claim text.