Pipeline having an integral cache which processes cache misses and loads data in parallel

A method of loading data from a cache to registers in a vector processor pipeline, the method comprising the steps of:

• a) requesting a data block from said cache;
• b) checking whether there is a hit in said cache for said block of data to be loaded, said hit indicating that said data block is in said cache, and a miss indicating said data block is not in said cache;
• c) driving said data block from said cache to said registers when there is a hit;
• and
• d) obtaining said data block from a memory when there is a miss and writing said obtained data block into said cache and said registers, wherein steps a, b, and c are repeated for subsequent data blocks after the step of checking for said data block indicates a miss;
• and wherein the step of the obtaining of said data block is performed during the repeating of steps a, b, and c for said subsequent data blocks.

A pipeline in computer processor for loading data entries in registers and storing data entries from said registers, the pipeline comprising:

• a cache memory for storing data;
• a loading device which loads data entries from said cache memory to said registers and which stores data entries from said registers in said cache memory with loading and storing data entries from and to said cache memory being pipelined;
• a determining device which determines when one of said data entries is a miss;
• a controller operating to obtain a return data entry corresponding to the one of the data entries determined to be a miss, the controller operating independently of the pipelining of data entries to and from the registers;
• a storage device coupled to the controller for storage of the return data entry;
• a filling device coupled to the storage device which fills the cache memory with said return data entry, said pipeline continuing to operate without stalling in the presence of missed data entries.