US 5,146,423 AGranted

Circuit arrangement for adding or subtracting operands coded in BCD-code or binary-code

AssigneeSiemens Aktiengesellschaft

InventorsHorst Fischer, Wolfgang Rohsaint

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Abstract

It is possible to add or subtract operands coded in binary coded decimal (BCD) code or in the binary code with the circuit arrangement upon employment of a single binary adder. In order to enable BCD operations, the BCD operations are supplied to the binary adder (DA) via input stages (EG1, EG2). The one input stage (EG1) inverts the allocated operand (A) when this operand has a minus sign. The other input stage (EG2) edits the allocated operand (B) such that, given positive operands, (A, B), the number 6 is added to the allocated operand (B) and the result is inverted given negative operands (A, B). Given operands in the binary code, the allocated operands are inverted when they are provided with a minus sign; otherwise, they are not influenced. After the operation of the edited operands (X, Y) in the binary adder (DA), a correction of the sum result (S) can be required given BCD operation. This is the case when a carry signal (C) in the binary operation in the binary adder (DA) has appeared at the most significant place of the sum result. In this case the number 6 is subtracted from the sum result (S) in an output stage (AGS). This leads to the corrected sum (R). Upon employment of a single binary adder, it is possible to add and to subtract BCD numbers and binary numbers with the circuit arrangement.

Claims11

Dependent claims

A circuit arrangement for adding or subtracting 4-bit first and second operands coded in one of binary coded decimal or binary code upon employment of a binary adder, comprising:

(a) a first input stage having an output connected to a first input of the binary adder, said first input stage receiving the first operand, said first input stage having means for adding the number 6 to said first operand given operations of binary coded decimal operands with positive operands;
means for adding the number 6 to said first operand given negative operands and negating the result of the addition;
means for not modifying said operand given different operational signs of the two operands and a positive operational sign of said first operand;
means for negating said first operand given different operational signals of the two operands given negative operational signal of said first operand;
means for negating said first operand but not otherwise modifying said first operand given operations of operands in the binary code with a negative said first operand;
(b) a second input stage for receiving the second operand, said second input stage having, when receiving a negative, second operand, means for negating the second operand but otherwise leaving the second operand unmodified, said second input stage having an output connected to a second input of the binary adder;
(c) an output stage connected to a sum output of the binary adder, said output stage having, given binary coded decimal operations of the first and second operands and an absence of a carry on a carry output of the binary adder, means for subtracting the number 6 from a sum result on the sum output of the binary adder in order to generate a corrected sum but otherwise said output stage through-connecting the sum result.

4 more elements

Dependencies are inferred from the claim text.