CMOS winner-take all circuit with offset adaptation

An adaptable circuit, communicating with a plurality of current-carrying lines, for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing, including:

• a plurality of MOS current mirrors, each of said current mirrors including an input node, an output node, a driving MOS current mirror transistor of a first conductivity type and a driven MOS current mirror transistor of said first conductivity type, the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a first voltage rail, the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of a capacitor, the gate of said driven MOS current mirror transistor connected to a floating node, a second electrode of said capacitor comprising a portion of said floating node, the drain of said driven MOS current mirror transistor comprising said output node and connected to the gate of said follower transistor;
• a pulldown transistor of a second conductivity type opposite to said first conductivity type associated with each of said current mirrors, each of said pulldown transistors having its source connected to a second voltage rail, and its gate connected to a common pulldown gate line;
• a pulldown gate bias transistor of said second conductivity type, having its source connected to said second voltage rail, its gate connected to a source of bias voltage;
• a follower transistor of said second conductivity type associated with each of said current mirrors, having its gate connected to the output of the current mirror with which it is associated, and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line;
• means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line, and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit, and for connecting said common pulldown gate line to a source of fixed voltage, and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit;
• and
• means for adjusting the charge on said floating node in response to the voltage on said output node during said adapting mode of said circuit;
• whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit.