US 5,142,247 A · Multiple frequency phase-locked loop clock generator with stable transitions between frequencies

Abstract

A phase-locked loop (PLL) clock generator circuit which is capable of changing the frequency of its outpt clock signal in a stable fashion. Selection of the frequency of the output clock signal is made by way of a selectable frequency divider coupled between the reference clock signal and an input of the PLL, with another frequency divider in the feedback loop of the PLL; each of these frequency dividers are selectable according to a signal on a select bus, translated by way of a ROM look-up table. The circuit also includes a multiplexer having a first input coupled to the PLL output, and a second input coupled to a stable clock signal, for example to the referenc clock signal or to the output of a fixed frequency PLL. The conrol input of the multiplexer is controlled by a state machine which monitors the select bus. Responsive to detection of a transition of the select bus, indicating a new frequency, the state machine issues a pulse to the control input of the multiplexer to cause it to select the stable clock signal for sufficient time to allow the PLL to acquire and lock onto the new frequency, after which the multiplexer again selects the PLL output as the output clock signal. As a result, the unstable and non-linear behavior at the PLL output does not appear at the output of the circuit, with a stable clock signal at a safe frequency appearing thereat during the PLL transitional cycles.

Claims28

Dependent claims

A clock generator circuit, comprising:

a phase-locked loop, coupled to receive a reference clock signal;
means, coupled to an input of said phase-locked loop and to a select input, for selecting a frequency multiple of said reference clock signal to be generated by said phase-locked loop;
a multiplexer, having a first input coupled to the output of said phase-locked loop, having a second input for receiving a stable clock signal, having an output, and having a control input for selecting said first or second input to be coupled to said output;
and
means, coupled to said select input of said selecting means, and to said control input of said multiplexer, for controlling said multiplexer to select said stable clock signal for a duration of time following a transition at said select input.

2 more elements

A circuit for generating a clock signal, comprising:

a phase-locked loop having a first input coupled to receive a reference clock signal;
a first frequency divider, coupled to an input of said phase-locked loop, and coupled to a select input, for selecting a frequency multiple of said reference clock signal to be generated by said phase-locked loop;
an output control circuit, coupled to receive the output of said phase-locked loop and a stable clock signal, having an output corresponding to the output of the circuit, for monitoring said select input for transitions thereat, and for applying said stable clock signal at its output for a selected duration following a transition at said select input.

Dependencies are inferred from the claim text.

Multiple frequency phase-locked loop clock generator with stable transitions between frequencies

Life of this patent

Multiple frequency phase-locked loop clock generator with stable transitions between frequencies

Life of this patent

Abstract

Claims28