US 5,140,554 AGranted

Integrated circuit fuse-link tester and test method

AssigneeTexas Instruments Incorporated

InventorsJohn F. Schreck, Phat C. Truong, David Tatman

Life of this patent

Estimating the term…

Loading patent…

Abstract

A test circuit for determining whether or not fuse-links of an integrated circuit have been opened or closed properly by, for example, a laser device. The test circuit of this invention, in one embodiment, includes a variable impedance, such as a P-channel transistor, connected between a voltage source and an output terminal, the impedance having one value with a first input applied to the variable impedance control terminal and having a second, larger value in response to a second input applied to the variable impedance control terminal. At least one programmable fuse-link and a gate are connected in series between the output terminal and a source of reference potential. A means for providing control inputs to the variable impedance is connected between a test mode input signal and the control terminal of the variable impedance. The means for providing control inputs to the P-channel transistor may include a second, current-mirror-connected P-channel transistor.

Claims16

Dependent claims

A test circuit, comprising:

a voltage source input;
a reference potential input;
a test mode signal input;
at least one address signal input;
an output node;
a variable impedance having first, second and third terminals, the impedance between said first and second terminals having at least one value in response to a first control input applied to said third terminal and having at least a second value in response to a second control input applied to said third terminal, said first terminal connected to said voltage source input, said second terminal connected to said output node;
at least one programmable fuse-link having first and second terminals;
at least one gate device having first, second and third terminals, said gate device being conductive and non-conductive between said first and second terminals in response to said address signal input applied to said third terminal, said first terminal of said gate device connected to said first terminal of said fuse-link;
said second terminal of said programmable fuse-link connected to one of said reference potential input and said output node and said second terminal of said gate device connected to the other of said reference voltage input and said output node;
and
means for providing said first and second control inputs to said third terminal of said variable impedance, said means having at least first and second terminals, said first terminal of said means connected to said third terminal of said variable impedance, said second terminal of said means connected to said test mode signal input.

8 more elements

A test circuit, comprising:

a voltage source input;
a reference potential input;
a test mode signal input;
at least one address signal input;
an output node;
a variable impedance having first, second and third terminals, the impedance between said first and second terminals having at least one value in response to a first control input applied to said third terminal and having at least a second value in response to a second control input applied to said third terminal, said first terminal connected to said voltage source input, said second terminal connected to said output node;
at least one programmable fuse-link having first and second terminals;
at least one gate device having first, second and third terminals, said gate device being conductive and non-conductive between said first and second terminals in response to said address signal applied to said third terminal, said first terminal of said gate device connected to said first terminal of said fuse-link;
said second terminal of said programmable fuse-link connected to said output node and said second terminal of said gate device connected to said reference potential input;
and
means for providing said first and second control inputs to said third terminal of said variable impedance, said means having at least first and second terminals, said first terminal of said means connected to said third terminal of said variable impedance, said second terminal of said means connected to said test mode signal input.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/574,835Filed 30 Aug 1990
Granted: 18 Aug 1992
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 29/027
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in fuses
G11C 17/18
In which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of…
G11C 29/02
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: detection or location of defective…
G11C 29/50
Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals: marginal testing, e.g. race, voltage…