Delay equalization emulation for high speed phase modulated direct digital synthesis

A direct digital synthesis (DDS) system comprising:

• an N-stage pipelined accumulator driven by a clock signal for processing increment data;
• first input means for receiving a first binary word representing a predetermined increment value, the first binary word consisting of a first ordered series of N groups of bits, each first-series group corresponding to a respective stage of the accumulator;
• second input means for receiving a second binary word representing a phase modulation increment value, the second binary word consisting of a second ordered series of M groups of bits, where M is a nonzero integer less than or equal to N, each second-series group corresponding to a respective stage of the accumulator;
• a series of M switch blocks, corresponding to the M most significant stages of the accumulator, respectively, each switch block coupled to the first input means to receive a respective one of the first series of groups of bits, coupled to the second input means to receive a respective one of the second series of groups of bits and coupled to the corresponding stage of the accumulator to provide increment data;
• each of the M switch blocks including means responsive to a binary select signal for selecting one of the first and second groups of bits as the increment data;
• a shift register having at least M stages driven by the clock signal, each one of M contiguous stages of the shift register having a Q output terminal coupled to a respective one of the switch blocks to provide the corresponding binary select signal;
• and
• means for loading a single bit into the shift register to provide a pulse so that, as the pulse propagates through the said M stages of the shift register, the select signals control each switch block to provide a second-series groups of bits to the corresponding stage of the accumulator and then switch back to providing the corresponding first-series group of bits after the pulse passes.

In a direct digital synthesis (DDS) system having an N-stage pipelined accumulator driven by a clock signal, a method of phase modulation comprising:

• providing an increment data word comprising a first ordered series of N groups of bits, each first-series group corresponding to a respective stage of the accumulator;
• providing a phase modulation data word comprising a second ordered series of M groups of bits, where M is a nonzero integer less than or equal to N, each second-series group corresponding to a respective stage of the accumulator;
• responsive to a first cycle of the clock signal:
• selecting a least significant one of the second series of groups;
• coupling the selected second-series group to the corresponding stage of the accumulator;
• selecting all of the first series of groups except a first-series group that corresponds in binary significance to the selected second-series group;
• and
• coupling the selected first-series groups to the respective corresponding stages of the accumulator;
• and
• responsive to each one of a next M-1 clock cycles:
• selecting a next least significant one of the second series of groups;
• coupling the selected second-series group to the corresponding stage of the accumulator;
• selecting all of the first series of groups except a first-series group that corresponds in binary significance to the selected first-series group;
• and
• coupling the selected first-series groups to the respective corresponding stages of the accumulator;
• thereby interleaving the phase modulation data word into the increment data provided to the accumulator.

A method according to claim -1 including:

• providing a predetermined Repeat Value;
• counting cycles of the clock signal;
• and
• comparing the number of counted clock cycles to the Repeat Value;
• and wherein
• a next clock cycle after the number of counted clock cycles equals the Repeat Value defines the first clock cycle, to begin interleaving the phase modulation data word after the Repeat Value number of clock cycles.

In a direct digital synthesis (DDS) system having a pipelined accumulator driven by a clock signal, the accumulator having N stages of Q bits per stage, a method of changing increment value comprising:

• (a) providing N storage elements of Q bit positions per storage element for storing increment data;
• (b) coupling each storage element to a respective one of the accumulator stages to provide stored increment data to the accumulator;
• (c) providing a new increment data word, the data word comprising an ordered series of N groups of Q bits per group, each group corresponding to a respective one of the storage elements and to a respective stage of the accumulator;
• (d) responsive to a first cycle of the clock signal:
• selecting a least significant one of the series of groups;
• storing the selected group in the corresponding storage element;
• and
• recirculating data previously stored in the other storage elements;
• and
• (e) responsive to each one of a next N-1 clock cycles:
• selecting a next least significant one of the series of groups;
• storing the selected group in the corresponding storage element;
• and
• recirculating data previously stored in the other storage elements, thereby sequentially changing each group of stored increment data to reflect the new increment data.