Systolic array image processing system
AssigneeHNC, Inc.
InventorsRobert W. Means, Horace J. Sklar
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Abstract
A systolic array of processing elements is connected to receive weight inputs and multiplexed data inputs for operation in feedforward, partially-- or fully-connected neural network mode or in cooperative, competitive neural network mode. Feature vector or two-dimensional image data is retrieved from external data memory and is transformed via input look-up table to input data for the systolic array that performs a convolution with kernal values as weight inputs. The convoluted image or neuron outputs from the systolic array are scaled and transformed via output look-up table for storage in the external data memory.
Claims5
A systolic system for performing a two-dimensional image processing convolution of pixel data with kernel data, the system comprising:
- a systolic array of processing elements, wherein each of said processing elements comprises a pixel data register, a kernel data register, a multiplier coupled to said pixel data register and said kernel data register for multiplying the contents of said registers, and an accumulator coupled to said multiplier for adding the results of said multiplication to the previous contents of the accumulator;
- wherein said pixel data registers are coupled in a plurality of rows, each row comprising an equal number of pixel data registers coupled in series such that a pixel data element entered into the input end register of said row is transmitted sequentially through the other registers of said row to the output end register of said row;
- and
- wherein said kernel data registers are coupled in a plurality of columns, each column comprising an equal number of kernel data registers coupled in series such that a kernel data element entered into the input end register of said column is transmitted sequentially through the other registers of said column to the output end register of said column;
- wherein there are N rows and N columns;
- output bus means comprising a plurality of members, each member of said plurality being coupled to the accumulators in the processing elements having pixel data registers in one of said rows and receiving the contents of said accumulators, said plurality being equal in number to the number of said rows;
- kernel input means comprising a plurality of members, each member of said plurality being coupled to the input end register of one column of kernel data registers and supplying kernel data to said input end register, said plurality being equal in number to the number of said columns;
- a first input for supplying pixel data;
- a second input for supplying pixel data;
- and
- multiplexer means coupled to said first input and said second input and to the input and registers of said rows of pixel data registers for transmitting pixel data from said first input and said second input to the input end registers of said rows;
- wherein said multiplexer means includes a plurality of multiplexers, each supplying pixel data to one of said rows and having an input coupled to said second input and having another input coupled to receive pixel data from another row;
- and
- said multiplexer means operates in sample intervals to apply data input to said another row from said second input each one sample interval out of N sample intervals, and from the data input from another row each N-1 sample intervals out of N sample intervals.
Dependencies are inferred from the claim text.