US 5,138,619 AGranted

Built-in self test for integrated circuit memory

AssigneeNational Semiconductor Corporation

InventorsPatrick P. Fasang, Walter F. Bridgewater

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Abstract

In a built-in self test ("BIST") circuit for on-chip testing of an integrated circuit memory, a control logic circuit is responsive to an external signal on a test select pin for controlling the BIST operations of the major circuit groups thereof. The major circuit groups include an address PRPG (pseudo-random pattern generator), which selectively furnishes test addresses or mission addresses to the memory; a data PRPG, which selectively furnishes test data or mission data to the memory; a PSA (parallel signature analyzer) PRPG, which furnishes mission data from the memory in normal mode and determines a signature in test mode; and a decoder, which compares the signature determined by the PSA PRPG with a known correct signature and sets a flag to indicate memory pass/fail. The BIST circuit is modular and extendable for any N-word by M-bit memory. To this end, a counter in the control logic circuit comprises a plurality of counter slices, the address PRPG comprises a plurality of address slices, the data PRPG comprises a plurality of data slices, and the PSA PRPG comprises a plurality of PSA slices. The BIST circuit is formed by replicating slices for the major circuit groups. Only certain feedback paths in the major circuit groups and certain control signal combinatorial circuits in the control logic require customization.

Claims15

Dependent claims

An integrated circuit self-testing memory having a clock input, a BIST (built-in self test) select input, and a BIST error flag output, comprising:

a random access memory;
an address PRPG (pseudo-random pattern generator) connected to said memory by a parallel address bus, said address PRPG comprising:
a plurality of substantially identical successively arranged address PRPG slices, said address PRPG slices having respective test address inputs obtained for each of said address PRPG slices other than a first one of said address PRPG slices from an output of an immediately preceding one of said address PRPG slices, and
an address PRPG feedback circuit having an output connected to an input of said first address PRPG-slice, and having inputs respectively connected to ones of said address PRPG slices;
a data PRPG connected to said memory by a parallel data input bus, said data PRPG comprising:
a plurality of substantially identical, successively arranged data PRPG slices, said data PRPG slices having respective test data inputs obtained for each of said data PRPG slices other than a first one of said data PRPG slices from an output of an immediately preceding one of said data PRPG slices, and
a data PRPG feedback circuit having an output connected to an input of said first data PRPG slice, and having inputs respectively connected to outputs of selected ones of said data PRPG slices;
a PSA (parallel signature analyzer) PRPG connected to said memory by a parallel data output bus, said data PRPG comprising:
a plurality of substantially identical, successively arranged PSA PRPG slices, and PSA PRPG slices having respective data inputs obtained from respective bits of said memory, and further having respective test signature inputs obtained for each of said PSA PRPG slices other than a first one of said PSA PRPG slices from an output of an immediately preceding one of said PSA PRPG slices;
a parallel signature output bus comprising outputs of said PSA PRPG slices;
and
a PSA PRPG feedback circuit having an output connected to an input of said first PSA PRPG slice, and having inputs respectively connected to outputs of selected ones of said PSA PRPG slices;
a decoder containing a predetermined known correct signature, said decoder having an input connected to said signature output bus for comparing a determined signature on said signature output bus with said known correct signature and setting the BIST error flag output to indicate memory pass/fail;
and
control logic connected to the BIST select input and the clock input, and having output control lines connected to said address PRPG, said data PRPG, said PSA PRPG, and said decoder for controlling the operation thereof and for providing a seed number to said data PRPG.

12 more elements

A method for designing a built-in self test circuit for an integrated circuit memory having an address bus of a preselected width and a data bus of a preselected width, comprising the steps of:

replicating an address slice a selected number of times in accordance with the width of said address bus;
serially interconnecting said replicated address slices to form an address PRPG (pseudo-random pattern generator), said replicated address slices forming the respective stages thereof and providing test address bits to said memory on their respective outputs;
providing a feedback signal to the first stage of said address PRPG, said feedback signal being determined from outputs of selected stages of said address PRPG;
replicating a data slice a selected number of times in accordance with the width of said data bus;
serially interconnecting said replicated data slices to form a data PRPG, said replicated data slices forming the respective stages thereof and providing test data bits to said memory on their respective outputs;
providing a feedback signal to the first stage of said data PRPG, said feedback signal being determined from outputs of selected stages of said data PRPG;
replicating a PSA (parallel signature analyzer) slice a selected number of times in accordance with the width of said data bus;
serially interconnecting said replicated PSA slices to form a PSA PRPG, said replicated PSA slices forming the respective stages thereof, and receiving on inputs thereof respective data bits from said memory, and providing signature bits on their respective outputs;
providing a feedback signal to the first stage of said PSA PRPG, said feedback signal being determined from outputs of selected stages of said PSA PRPG;
and
providing a known correct signature for comparison with said signature bits to determine memory pass/fail.

8 more elements

Dependencies are inferred from the claim text.