Controlled slew rate buffer

A controlled slew rate buffer comprising a driver receiving voltage from a voltage along a voltage supply line, the driver comprising at least one of (1) first and second VSS voltage sources and (2) first and second VDD voltage sources and including feedback apparatus which senses voltage differences between at least one of the first and second voltage sources and slows the speed of the buffer in response to said voltage differences, and wherein said driver includes first and second transistors of the same type, the first transistor receiving an input from a first voltage supply and having an output connected to a pad and the second transistor receiving an input from a second voltage supply and having its gate connected to the first voltage supply and its output connected to the gate of the first transistor.

A controlled slew rate buffer comprising a driver receiving voltage along a voltage supply line, and including feedback apparatus which senses a noise level along the voltage supply line and slows the speed of the buffer when the noise level passes a given threshold and wherein said driver comprises:

• first and second transistors of the P type, the first transistor receiving an input from a first voltage supply and having an output connected to a pad and the second transistor receiving an input from a second voltage supply and having its gate connected to the first voltage supply and its output connected to the gate of the first transistor;
• and
• third and fourth transistors of the N type, the third transistor receiving an input from a third voltage supply and having an output connected to a pad and the fourth transistor receiving an input from a fourth voltage supply and having its gate connected to the third voltage supply and its output connected to the gate of the third transistor.

A controlled slew rate buffer comprising a driver receiving voltage from a voltage along a voltage supply line, the driver comprising at least one of (1) first and second VSS voltage sources and (2) first and second VDD voltage sources and including feedback apparatus which senses voltage differences between at least one of the first and second voltage sources and slows the speed of the buffer in response to said voltage differences, and wherein said driver comprises:

• first and second transistors of the P type, the first transistor receiving an input from a first voltage supply and having an output connected to a pad and the second transistor receiving an input from a second voltage supply and having its gate connected to the first voltage supply and its output connected to the gate of the first transistor;
• and
• third and fourth transistors of the N type, the third transistor receiving an input from a third voltage supply and having an output connected to a pad and the fourth transistor receiving an input from a fourth voltage supply and having its gate connected to the third voltage supply and its output connected to the gate of the third transistor.

A controlled slew rate buffer comprising a driver receiving voltage along a voltage supply line, and including feedback apparatus which senses a noise level along the voltage supply line and slows the speed of the buffer when the noise level passes a given threshold, and also including a pre-driver comprising a split inverter and a non-linear resistor disposed between the two parts of the inverter.

A controlled slew rate buffer comprising a driver receiving voltage from a voltage along a voltage supply line, the driver comprising at least one of (1) first and second VSS voltage sources and (2) first and second VDD voltage sources and including feedback apparatus which senses voltage differences between at least one of the first and second voltage sources and slows the speed of the buffer in response to said voltage differences, and also including a pre-driver comprising a split inverter and a non-linear resistor disposed between the two parts of the inverter.