Correlated coarse position error processor

Abstract

A technique for overcoming the difficulties that arise from the transition between coarse and fine loop control. Coarse and fine phase locked loops, each having a respective latch provide a coarse number in the range 000.0.degree.-359.9.degree. and a fine number in the range of 0.0000.degree.-0.9999.degree.. The coarse number is offset relative to the fine number so that the least significant digit (tenths digit) of the coarse number is always less than the most significant digit (tenths digit) of the fine number over the entire range of motion. The fine number latch is clocked by a reference clock (ZDS) while correlation circuitry provides a clock signal for the coarse number latch. The correlation circuitry generates the clock signal when the tenths digit of the coarse number agrees with the latched fine number. The result is a latched fine number and a coarse number that is latched when it correlates with the fine number (tenths digits agree). A fine error is provided by comparing the fine PLL counter data against the fine angle command data. A correlated coarse error is produced by comparing the coarse command and the correlated coarse number (subtracting and scaling). The fine error and the correlated coarse error are communicated to the two poles of an analog switch, and the fine error is selected whenever the correlated coarse error is less than a predetermined threshold.

Dependencies are inferred from the claim text.