Fast-acting current comparator
AssigneeAnalog Devices, Inc.
InventorKenneth Deevy
Life of this patent
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AssigneeAnalog Devices, Inc.
InventorKenneth Deevy
Estimating the term…
A comparator for use in an A/D converter such as an algorithmic type. The circuit includes a push-pull inverter gain stage having two series-connected MOSFETs. The input of this inverter is driven by a signal from a preceding current-comparison stage where an input current is compared to a reference current to set the signal level on an input node of the inverter. The trigger point of the inverter is altered by an additional MOSFET, connected in parallel with one of the inverter MOSFETs, and having its gate controlled by the output of a bias voltage control circuit. This circuit includes a control inverter stage matched to the comparator inverter and driven by a control current-comparison circuit matched to the corresponding comparator current-comparison circuit. The input and output nodes of the control inverter are connected to the inputs of an op-amp the output of which controls the gate voltage of an additional MOSFET in parallel with one of the control inverter MOSFETs so as to force the input and output nodes to be of equal voltage. The resulting op-amp output signal serves as the bias signal for the additional MOSFET in parallel with one of the comparator inverter MOSFETs, and sets the trigger point of the comparator inverter at a level equal to the balance point of the preceding current-comparison stage, thereby assuring fast transition times.
A fast-acting current comparator comprising:
A current comparator capable of fast transitions between high and low output states comprising:
The method of obtaining fast response from a current comparator having a current-comparison stage wherein an input current is compared to a reference current to produce a comparison signal which is applied to an input node of a first complementary MOSFET inverter gain stage having a transfer characteristic with a high-gain region establishing a trigger point at which the transition between high and low output levels occurs;
Dependencies are inferred from the claim text.