US 5,134,616 A · Dynamic RAM with on-chip ECC and optimized bit and word redundancy

Abstract

A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed. At the same time, having a set of interrelated bits in the SRAM compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

Claims36

Dependent claims

A memory, comprising:

a first array of memory cells having a first plurality of word lines, a first plurality of bit lines, and a first plurality of redundant bit lines;
a first plurality of data lines;
switching means for coupling selected ones of said plurality of redundant bit lines of said first array and selected ones of said plurality of bit lines of said first array to said first plurality of data lines;
a separate array of redundant memory cells comprising a second plurality of word lines and a second plurality of bit lines;
address means coupled to said first plurality of word lines of said first array of memory cells and to said second plurality of word lines of said separate array of redundant memory cells for accessing an X-bit error correction word comprising data bits and check bits from one of said first array of memory cells and said separate array of redundant memory cells;
error correction circuitry coupled to said first plurality of data lines and to said plurality of bit lines of said separate array of redundant memory cells, for reading said accessed X-bit error correction word from one of said first plurality of data lines and said separate array of redundant memory cells and correcting any faulty data bits therein;
and output means coupled to said error correction circuitry for providing said data bits as said accessed X-bit error correction word as corrected by said error correction circuitry for external read-out.

4 more elements

An architecture for at least part of an integrated circuit chip, comprising:

an array of memory cells disposed on a first portion of the integrated circuit chip, comprising a plurality of word lines, a plurality of bit lines, a first plurality of memory cells, each of said first plurality of memory cells being coupled to one of said plurality of word lines and to one of said plurality of bit lines, a plurality of redundant bit lines, and a second plurality of memory cells, each of said second plurality of memory cells being coupled to one of said plurality of word lines and one of said plurality of redundant bit lines;
a first plurality of data lines;
switching means for coupling selected ones of said plurality of redundant bit lines and said plurality of bit lines to said first plurality of data lines;
an independent word line redundancy array disposed on a second portion of the integrated circuit chip spaced from said first portion, said independent word line redundancy array having a plurality of word lines and a plurality of bit lines;
an error detection and correction means coupled to said first plurality of data lines and to said plurality of bit lines of said independent word line redundancy array for reading and correcting an error correction word comprising a plurality of data bits and a plurality of check bits;
and
a buffer coupled to said error detection and correction means for temporarily storing said error correction word.

4 more elements

A memory chip, comprising:

an array of memory cells interconnected by a plurality of word lines, a first plurality of bit lines, and a plurality of redundant bit lines,
means coupled to said plurality of word lines, said plurality of bit lines, and said plurality of redundant bit lines for simultaneously addressing a first predetermined number X of said first plurality of bit lines so as to access an X-bit error correction word, while also simultaneously addressing a second predetermined number N of said plurality of redundant bit lines,
a first set of X+N data lines coupled to at least said first predetermined number X of said first plurality of bit lines and to said second predetermined number N of said plurality of redundant bit lines,
a second set of X data lines, and
first switching means for selectively coupling said first set of X+N data lines to said second set of X data lines, so that signals originating from one or more of said second predetermined number N of said plurality of redundant bit lines are sent to said second set of X data lines in place of signals originating from any one or more of said first predetermined number X of said first plurality of bit lines that are faulty.

2 more elements

Dependencies are inferred from the claim text.

Dynamic RAM with on-chip ECC and optimized bit and word redundancy

Life of this patent

Dynamic RAM with on-chip ECC and optimized bit and word redundancy

Life of this patent

Abstract

Claims36