MOSFET with substrate source contact
AssigneeMotorola, Inc.
InventorsRobert J. Johnsen, Paul W. Sanders
Life of this patent
Estimating the term…
Abstract
A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-, P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.
Claims11
A vertical MOSFET device comprising:
- a semiconductor substrate having first and second opposed surfaces;
- a drain region adjacent the first surface, a channel forming region underlying the drain region, a source region underlying the channel forming region and a gate dielectric and electrode on a portion of the channel forming region between the source and drain regions for modulating the conductivity therebetween;
- and
- a buried ohmic contact shorting part of the channel forming region to the underlying source region.
A semiconductor device comprising:
- a semiconductor substrate having first and second opposed principal surfaces;
- a vertical MOSFET in the substrate, having source, drain, and gate for forming a channel permitting current flow between a source contact on the second surface and a drain contact on the first surface;
- and
- a buried ohmic contact within the substrate shorting the source to part of an internal region of the substrate in which the channel is formed.
A semiconductor device comprising:
- a first semiconductor region of a first conductivity and type;
- a second semiconductor region on the first semiconductor region and of a second conductivity and of a second type opposite the first type;
- a third semiconductor region on the second semiconductor region and of a third conductivity and of the first type;
- a fourth semiconductor region in the third semiconductor region and of a fourth conductivity and of the first type and extending to an upper surface of the third region;
- a first cavity having first and second sidewalls extending from the upper surface to the first region, wherein portions of the first and second regions are exposed in the first cavity;
- a first dielectric on a first portion of the second region exposed in the first cavity;
- a conductor on a first portion of the first region and a second portion of the second region exposed in the first cavity and ohmically contacting the first and second regions but not the third region;
- and
- a gate electrode on a second dielectric formed on the sidewalls of a second cavity extending from the upper surface to the first region, a source electrode contacting the first region and a drain electrode contacting the fourth region.
Dependencies are inferred from the claim text.