Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

A data processor including a plurality of information processing units, each connected in common to receive a first clock signal, for processing information synchronously with each other, each information processing unit comprising:

• clock generating means connected to receive said first clock signal, which has a first potential level and a second potential level different from said first potential level, said first and second potential levels being repeated substantially with a first duty cycle and at a first frequency, for generating at least a second clock signal which is substantially in phase with said first clock signal and which has a third potential level and a fourth potential level different from said third potential level, said third and fourth potential levels being repeated substantially with a second duty cycle and at a second frequency;
• arithmetic means, connected to receive said second clock signal, for subjecting input data to a desired logical operation and for delivering output data;
• and
• interface means, connected to receive said second clock signal, for controlling synchronous transfer of output data from said arithmetic means to arithmetic means in another information processing unit using said second clock signal and for receiving by synchronous transfer data corresponding to output data from an arithmetic means of another information processing unit, wherein said clock generating means comprises a clock generating section for generating at least one second clock signal which is substantially in phase with at least one first clock signal and which has a predetermined duty cycle, a phase comparator for making a comparison between the respective phases of two input signals, a low-phase filter, a voltage control oscillator, and a 1/N frequency divider, the output terminal of said 1/N frequency divider being connected to both one input terminal of said phase comparator and said clock generating section, the other input terminal of said phase comparator being supplied with said first clock signal, the output terminal of said phase comparator being connected to the input terminal of said low-pass filter, the output terminal of said low-pass filter being connected to the input terminal of said voltage controlled oscillator, and the output terminal of said voltage controlled oscillator being connected to the input terminal of said 1/N frequency divider.

A data processing apparatus, comprising:

• clock generating means, connected to receive a first clock signal having a first clock frequency, for generating a second clock signal which is substantially in phase with said first clock signal and has a second frequency;
• and
• a logic device, connected to receive said second clock signal from said clock generating means, for subjecting input data to a logical operation;
• said clock generating means including:
• (i) oscillating means, having a first input to which said first clock signal is supplied, a second input and an output from which there is provided a further clock signal having a frequency, for comparing the respective phases of signals supplied to said first and second inputs and for controlling the frequency of said further clock signal in accordance with a difference in said respective phases;
• (ii) a frequency divider for dividing the frequency of said further clock signal by a predetermined integer to produce at an output said second clock signal which is supplied to said logic device;
• and
• (iii) a feedback path connecting the output of said frequency divider to said second input of said oscillating means to supply a signal thereto.

A data processing apparatus, comprising:

• clock generating means, connected to receive a first clock signal having a first clock frequency, for generating a second clock signal which is substantially in phase with said first clock signal and has a second frequency;
• and
• a logic device, connected to receive said second clock signal from said clock generating means, for subjecting input data to a logical operation;
• said clock generating means including:
• (i) oscillating means, having a first input to which said first clock signal is supplied, a second input and an output from which there is provided a further clock signal having a frequency, for comparing the respective phases of signals supplied to said first and second inputs and for controlling the frequency of said further clock signal in accordance with a difference in said respective phases;
• (ii) a clock generator responsive to said further clock signal produced by said oscillating means for generating an output clock signal whose rise timing and fall timing are determined by the rise timing of said further clock signal, said output clock signal being supplied to said logic device as said second clock signal;
• and
• (iii) a feedback path connecting the output of said clock generator to said second input of said oscillating means to supply a signal thereto.

A data processing apparatus, comprising:

• clock generating means, connected to receive a first clock signal having a first clock frequency, for generating a second clock signal which is substantially in phase with said first clock signal and has a second frequency;
• and
• a logic device, connected to receive said second clock signal from said clock generating means, for subjecting input data to a logical operation;
• said clock generating means including:
• (i) oscillating means for generating a further clock signal having a frequency which is a multiple of said first frequency;
• (ii) a frequency divider for dividing the frequency of said further clock signal by a predetermined integer to produce said second clock signal which is supplied to said logic device;
• and
• (iii) control means responsive to a difference in phase between said first clock signal and at least a signal based on said second clock signal for controlling said oscillating means so that the duty of said second clock signal is made equal to a rated duty with each rising and falling edge of said second clock signal being determined by a rising edge of said further clock signal.

A data processing apparatus, comprising:

• a phase comparator, connected to receive a first clock signal having a first frequency and a second clock signal, for producing a signal representing a difference between the respective phases of said first and second clock signals;
• a low pass filter for producing a voltage signal whose magnitude is determined by the signal produced by said phase comparator;
• a voltage controlled oscillator connected to be controlled by the voltage signal produced by said low pass filter to produce a third clock signal whose frequency is a multiple of said first frequency;
• a frequency divider connected to said voltage controlled oscillator for dividing the frequency of said third clock signal by a predetermined integer to produce an output clock signal having a duty which is determined by the frequency of said third clock signal;
• a feedback path connected between said frequency divider and said phase comparator to supply said second clock signal to said phase comparator;
• and
• a logic device, connected to receive said output clock signal from said frequency divider, for subjecting input data to a logical operation.