US 5,132,935 A · Erasure of eeprom memory arrays to prevent over-erased cells

Abstract

The device and process of this invention provide for eliminating reading errors caused by over-erased cells by subsequently applying alternating erasing and programming pulses to the cells of an EEPROM array, starting with relatively high-energy-level erasing and programming voltages, decreasing the energy-level of each of the alternating erasing and programming voltages. The initial, relatively high-energy-level pulses should have sufficient energy to cause all of the cells to be programmed and to cause all of the cells to be over-erased. The energy-levels are decreased until electron transfer between floating gate and a source or drain region ceases. As the energy-levels are decreased, the threshold voltage range of the memory cells is compacted. The final threshold voltages are distributed within a preselected narrow range of positive values that are less than a predetermined wordline select voltage.

Claims20

Dependent claims

A method for erasing a memory cell having a floating gate, at least one control terminal, a source terminal and a drain terminal, said memory cell programmable and erasable by applying programming and erasing electrical energy pulses between said control terminal and at least one of said source and drain terminals, said memory cell readable by applying a preselected read voltage between said control terminal and at least one of said source and drain terminals, the method comprising:

initially applying first alternating said programming and erasing electric energy pulses between said control terminal and said at least one of said source and drain terminals;
then applying second alternating said programming and erasing electric energy pulses between said control terminal and said at least one of said source and drain terminals, said second alternating pulses having decreased energy-levels as compared to said first alternating pulses, until said cell has an erased threshold voltage having the same polarity as said preselected read voltage and that is less than said preselected read voltage.

A non-volatile memory array, comprising:

memory cells arranged in rows and columns, each said memory cell having a source-drain path between first and second terminals and having a control-gate terminal
a source-column line connected to each said first terminal of each said memory cell in a said column;
a drain-column line connected to each said second terminal of each said memory cell in a said column;
a wordline connected to each said control-gate terminal of each said memory cell in a said row;
each said memory cell having a floating-gate conductor insulated from said source-drain path and from said control gate terminal, said floating-gate conductor being programmable and erasable by programming and erasing pulsed electric fields adjacent said floating-gate conductor, said programming and erasing pulsed electric fields related to pulsed programming and erasing voltages applied between said control-gate terminal and at least one of said first and second terminals;
a column decoder connected to said source-column lines and said drain column lines and a wordline decoder connected to said wordlines for providing said pulsed programming and erasing voltages to said memory cells via said wordlines and at least one of said source-column lines and said drain-column lines;
and
an erase control circuit for causing said column decoder and said wordline decoder to provide said pulsed programming and erasing voltages to said memory cells via said wordlines and at least one of said source-column lines and said drain-column lines, said control circuit initially causing relatively high-energy-level programming and erasing pulsed electric fields directed alternately toward or away from a surface of said floating gates;
said control circuit then causing said alternating programming and erasing pulsed electric fields to have decreased energy-levels.

6 more elements

A method for erasing a memory-cell array prior to programming said array, each said memory cell including a floating gate, the method comprising:

initially causing alternating erasing and programming pulsed electric fields adjacent said floating gates of said memory cell array, said pulsed electric fields initially having relatively high energy-level;
then causing said alternating erasing and programming pulsed electric fields to have decreased energy-level until each said memory cell is erased but not over-erased.

Dependencies are inferred from the claim text.

Erasure of eeprom memory arrays to prevent over-erased cells

Life of this patent

Erasure of eeprom memory arrays to prevent over-erased cells

Life of this patent

Abstract

Claims20