Interleaved bridge converter

In a full-bridge DC-DC power converter coupled to an input DC voltage source for converting input power and supplying DC output voltage to a load in which said converter consists of

• first, second, third and fourth field-effect transistors each of which comprises a gate for controlling the switching of said transistor off and on and a source-drain path which provides a current path when said transistor is switched on,
• first and second secondary windings that are wound with opposite polarity windings and are coupled to each other at a junction point of like polarity,
• output DC voltage source means coupled to said junction point of said first and second secondary windings,
• a common series current path coupled to conduct current through said source-drain paths of said first and fourth transistors during one instance of time and through said source-drain drain paths of said second and third transistors during another instance of time, wherein said series current path comprises coupling means for inductively coupling electric magnetic energy from said series current path to said first and second secondary windings, and
• timing control means coupled to the gates of all of said field-effect transistors constructed to supply gating signals to said gates of said transistors for controlling the switching of transistors on and off,
• the improvement wherein the coupling means comprises first and second primary windings connected in series with each other so as to form the only elements in said series current path, each of said first and second primary windings being coupled to only one of said first and second secondary windings, and
• wherein no shunt current path elements are coupled to said series current path, and said first and second primary windings are wound such that they are of an opposite polarity with respect to each other and are also of opposite polarity with respect to that one of said secondary windings to which each of said respective primary windings is coupled, and wherein said timing control means is constructed to supply said gating signals such that the voltages across all of said source-drain paths are approximately zero whenever any of said switching of said transistors occurs.