Large fault tolerant packet switch particularly suited for asynchronous transfer mode (ATM) communication
AssigneeBell Communications Research, Inc.
InventorArturo Cisneros
Life of this patent
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AssigneeBell Communications Research, Inc.
InventorArturo Cisneros
Estimating the term…
Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). An ATM cell applied to an input port of an interface module contains a data field and a virtual channel identifier (VCI) field. The VCI is translated by the interface module into a new VCI, to identify an output of the virtual channel for the switch and appends to the cell an additional routing header which will be used strictly for internal use in routing the entire cell through the switch and which includes distinct first and second portions.
Apparatus for a packet switch comprising:
Apparatus for a packet switch comprising:
In a packet switch having a plurality of input modules each providing a plurality of input ports and having a plurality of outputs, a plurality of output modules each having a plurality of inputs and providing a plurality of output ports, and a plurality of cross-point switching circuits each being connected to a corresponding output of each of said input modules and to a corresponding input to each of said output modules, and wherein each of said incoming packets has first and second distinct address portions and a data portion therein, a method for routing packets through said switch comprising the steps of:
In a packet switch having "k" substantially identical input modules each providing "n" separate input ports and having "m" separate outputs, "k" substantially identical output modules each having "m" separate inputs and providing "n" separate output ports, and "m" substantially identical k-by-k cross-point switching circuits each being connected to a corresponding output of each of said input modules and to a corresponding input to each of said output modules, wherein all the corresponding outputs have the same numerical ranking and all of the corresponding inputs having the same numerical ranking, and wherein each of said incoming packets has first and second distinct address portions and a data portion therein, a method for routing packets through said switch comprising the steps of:
Dependencies are inferred from the claim text.