Signal delay circuit for minimizing the delay time dependence on power supply voltage variation
AssigneeSamsung Electronics Co., Ltd.
InventorYun-Seung Sin
Life of this patent
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Abstract
A signal delay circuit includes a driving circuit for driving an output signal with a voltage swing voltage between a supply voltage and a ground voltage. The signal delay circuit further includes a varactor load which is coupled to the output signal and has a capacitance which increases according to the supply voltage within a variation range of the supply voltage. The varactor load keeps the delay characteristic of the signal propagation circuit independent of the change of the supply voltage, thereby ensuring high speed operation and improved reliability of the CMOS semiconductor integrated circuit.
Claims13
A signal delay circuit comprising:
- driving circuit means, which is coupled between a supply voltage and a first reference voltage and includes a pull-up PMOS transistor and a pull-down NMOS transistor having respective predetermined threshold voltages, for driving an output signal having a voltage swing between said supply voltage and said first reference voltage to a common drain node of said transistors in response to at least one input signal;
- and
- varactor load means coupled to said common drain node, having a capacitance which increases according to the increase of said output signal voltage of said common drain node within a variation range from the threshold voltage of said pull-down NMOS transistor to said supply voltage.
A signal delay circuit comprising
- driving circuit means, which is coupled between a supply voltage and a first reference voltage and includes a pull-up PMOS transistor and a pull-down NMOS transistor having respective predetermined threshold voltages, for driving an output signal having a voltage swing between said supply voltage and said first reference voltage to a common drain node of said transistors in response to at least one input signal;
- and
- varactor load means including a PMOS varactor having a P+source electrode coupled to said output signal applied to said common drain node and a gate electrode coupled to said first reference voltage.
Dependencies are inferred from the claim text.