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AssigneeMicron Technology, Inc.
InventorsAngus C. Fox, III, Warren M. Farnworth
Estimating the term…
A high-density package containing identical multiple IC chips is disclosed. The package is assembled from submodules interleaved with frame-like spacers. Each submodule comprises a rectangular, wafer-like substrate. The substrate has a planar metalization pattern, comprising conductive traces, on its upper surface. A single memory chip is face-bonded to this metalization pattern. Each of the traces extends from beneath a chip bonding pad, with which it is in electrical communication, and runs to the substrate periphery, where it terminates in one or more solderable package interconnection pads (PIP's). Each PIP is associated with a single substrate via, which extends through the pad to the lower surface of the substrate. During package assembly, a spacer is adhesively bonded to the peripheral upper surface of each sub-module, with the frame surrounding the chip. The spacer also has a plurality of vias which are coincident and coaxial with the substrate vias, with the spacer vias being of larger diameter. Each spacer-equipped module is then adhesively bonded to the others to form a stack. The upper-most spacer-equipped module is fitted with a non-metalized (capping) substrate. In order to electrically interconnect the related traces of all sub-modules, the package is placed in a solder bath, and a partial vacuum is applied simultaneously to one end of all tubes formed from the coincident, stacked vias, filling them with molten solder.
A high-density electronic package comprising a plurality of sub-modules stacked one on top of the other, each of said sub-modules including a wafer-like substrate having upper and lower planar surfaces, a planar metalization pattern affixed to said upper surface to which an integrated circuit chip is bonded, said metalization pattern consisting of conductive traces, each of which leads from a bonding pad on the chip to at least one substrate via which penetrates the substrate perpendicular to said upper and lower surfaces, and a frame-like spacer which is adhesively bonded to the upper surface of said substrate, said spacer having spacer vias which are coincident and substantially coaxial with the substrate vias, said spacer vias being of larger diameter than said substrate vias, and a capping substrate for capping the upper-most of the stacked sub-modules, said capping substrate having capping vias which are coincident with and substantially coaxial with said substrate vias and said spacer vias, but of larger diameter than said substrate vias, and a plurality of solder columns formed within the resulting stacks of coincident substrate, spacer and capping vias, which electrically interconnect traces of the various sub-modules and provide external electrical connection points on the upper surface of the capping module and the lower surface of the lower-most module.
A high-density electronic package comprising a plurality of sub-modules, a capping substrate, and a plurality of solder columns which electrically interconnect said sub-modules and provide external electrical connection;
Dependencies are inferred from the claim text.