Adaptive phase lock loop system

An adaptive phase lock loop system comprising:

• a buffer memory for storing a digital input signal;
• a phase detector for comparing a phase of the digital input signal and a phae of a reference signal;
• a loop filter coupled with an output of said phase detector;
• a digital voltage controlled oscillator providing a VCO output as the reference signal to said phase detector, said digital voltage controlled oscillator including
• a center frequency generator providing a center frequency of said digital voltage controlled oscillator,
• a first adder to provide a sum of an output of said loop filter and an output of said center frequency generator,
• an accumulator accumulating an output of said first adder,
• an initial phase generator providing an initial phase of said digital voltage controlled oscillator,
• a second adder providing a sum of an output of said accumulator and an output of said initial phase generator,
• a cosine converter converting an output of said second adder to a cosine waveform for providing the reference signal of the VCO output,
• an initial phase difference caclulator, coupled with the output of said loop filter, said initial phase difference calculator updating the initial phase output fromm said initial phase generator,
• a center frequency difference calculator, coupled with the output of said loop filter, said initial phase difference calculator updating the initial phase output from said initial phase generator according to the output of said loop filter,
• a center frequency difference calculator, coupled with the output of said loop filter, said center frequency difference calculator updating the center frequency output from said center frequency generator accordiing to the output of said loop filter, and
• a mode control means for switchin an operation state between an initial training mode and a normal opeation mode;
• wherein said initial training mode repetitively adjusts the initial phase and the center frequency of said initial phase difference calculator and said center frequency different calculator so that the initial phase and the center frequency become optimum to complete a lock-in state for the input signal of said buffer memory, respectively, and said normal operation mode providing a reference signal of the VCP output so that said reference signal is phase-locked with the input signal by using the initial phase and center frequency optimized in said initial training mode.