Josephson integrated circuit having an output interface capable of providing output data with reduced clock rate

A Josephson integrated circuit for performing digital logic operations with the capability of outputting the result of the operations with reduced clock rate, comprising:

• a Josephson logic processor of Josephson devices, said Josephson logic processor being operated at a first clock rate and given with input data for carrying out a logic operation of the input data, said Josephson logic processor producing output data representing a result of the logic operation and a status signal indicating a status of the logic operation;
• latch means comprising Josephson devices operated at the first clock rate for receiving the output data from the Josephson processor, said latch means being supplied with the status signal from the Josephson processor for holding the output data therein, said latch means being further supplied with a clear signal for resetting the output data therefrom;
• and
• data output means comprising Josephson devices operated in response to a second clock rate that is slower than the first clock rate, said data output means having an output terminal and supplied with the output data held in the latch means for passing the output data to the output terminal at the second clock rate, said data output means further producing the clear signal at the second clock rate.