Method of manufacturing edge connected semiconductor die
AssigneeMicron Technology, Inc.
InventorRandal W. Chance
Life of this patent
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Abstract
Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, allowing the entire top surface of the die to be passivated, a better contact configuration, and more convenient assembly for packaging.
Claims16
Method of forming an integrated circuit device having die bond locations on a perimeter of a die, the method comprising:
- a) preparing a semiconductor wafer, which includes a semiconductor substrate and a plurality of dice, each die being defined by a perimeter, and having circuitry on a face of the die;
- b) forming a plurality of depressions in the substrate, the depressions each extending from locations on the faces to said perimeter;
- c) depositing conductive material in said depressions to form wirebond pads;
- d) forming a first group of contacts, contacting said wirebond pad to said circuitry within the die;
- e) passivating the dice by applying a protective dielectric over the dice;
- and
- f) separating the dice, thereby exposing edges of said depression, with the conductive material in said depressions forming die bond locations along said exposed edges.
Method of forming integrated circuit electronic components, characterized by:
- a) forming circuitry on a semiconductor wafer, said circuitry including die bond locations;
- b) forming a passivation layer over said circuitry;
- and
- c) exposing the die bond locations by use of a wafer saw.
Dependencies are inferred from the claim text.