Method and apparatus for semiconductor device passivation

Abstract

A passivation layer of dielectric material disposed on the top surface of the semiconductor device prevents the metallized patterns on the semiconductor substrate from being exposed to chemical attack. This layer also provides for improved metal electro-migration resistance through the well-known mechanism of grain boundary pinning. The semiconductor device substrate includes a dielectric layer which is disposed along the surface over the electrode metallization. The semiconductor substrate includes metallized regions on top of the dielectric layer which is disposed over the substrate surface and the electrodes thereon. These metallized regions form capacitors to the semiconductor electrodes and capacitively couple electrical input and output signals to the electrodes from external electronic apparatus.

Dependencies are inferred from the claim text.