Method and apparatus for autoranging, quadrature signal generation, digital phase reference, and calibration in a high speed RF measurement receiver

An improved autoranging circuit for selecting one of a plurality of predetermined gain stages of amplification for an input signal, comprising:

• analog to digital (A/D) converter means for providing a digital signal sample of said input signal;
• timing means for timing a predetermined number of accumulation cycles;
• memory means responsive to said digital signal sample of said input signal and an accumulated input signal value for providing as an output, for each one of said accumulation cycles, a sum of absolute values of said digital signal sample value and said accumulated input signal from a previous accumulation cycle;
• storage means for storing said sum from said memory means as said accumulated input signal value for a next accumulation cycle;
• programmed logic means responsive to said accumulated input signal value after said predetermined number of said accumulation cycles for providing gain selection signals;
• and
• a selectively variable gain amplifier responsive to said gain selection signals for selecting one of said plurality of predetermined gain stages of amplification for said input signal, thereby providing a gain ranged output signal.

A method for calibrating a complex signal detection means, said complex signal detection means providing inphase and quadrature phase output signals in response to an input signal, comprising the steps of:

• in response to a calibration command, generating a calibration reference signal;
• providing said calibration reference signal as said input signal to said complex signal detection means;
• generating timing signals for causing said complex signal detection means to convert said input signal into an inphase output signal and a quadrature phase output signal;
• in response to said calibration command, providing a phase offset signal corresponding to a predetermined phase offset for said calibration reference signal;
• in response to said phase offset signal, altering the timing of said timing signals for said complex signal detection means so that said complex signal detection means provides phase-offset inphase and quadrature phase output signals which are shifted in phase by an amount corresponding to said predetermined phase offset;
• providing said phase-offset inphase and quadrature phase output signals to a computing device;
• and
• calculating a calibration correction for gain and orthogonality for said complex signal detection means in response to said phase-offset inphase and quadrature phase output signals.

An apparatus for calibration of a complex signal detection means, said complex signal detection means providing inphase and quadrature phase output signals in response to an input signal, comprising:

• means responsive to a calibration command for generating a calibration reference signal;
• means for providing said calibration reference signal as said input signal to said complex signal detection means;
• timing signal means for generating timing signals for causing said complex signal detection means to convert said input signal into an inphase output signal and a quadrature phase output signal;
• phase offset signal means responsive to said calibration command for providing a phase offset signal corresponding to a predetermined phase offset for said calibration reference signal;
• timing signal altering means responsive to said phase offset signal for altering the timing of said timing signals for said complex signal detection means so that said complex signal detection means provides phase-offset inphase and quadrature phase output signals which are shifted in phase by an amount corresponding to said predetermined phase offset;
• means for providing said phase-offset inphase and quadrature phase output signals to a computing device;
• and
• means for calculating a calibration correction for gain and orthogonality for said complex signal detection means in response to said phase-offset inphase and quadrature phase output signals.

An apparatus for calibration of a complex signal detection means, said complex signal detection means providing inphase and quadrature phase output signals in response to an input signal, comprising:

• means for providing a precision timed clock signal;
• a counter for counting occurrences of said clock signal;
• a read only memory (ROM) responsive on some of its address lines to the states of said counter for generating timing signals from a first portion of memory;
• means responsive to a calibration command for generating a calibration reference signal;
• means for providing said calibration reference signal as said input signal to said complex signal detection means;
• phase offset signal means responsive to said calibration command for providing a phase offset signal as other inputs for other address lines of said ROM, said phase offset signal corresponding to a predetermined phase offset for said calibration reference signal;
• said ROM being responsive to said phase offset signal for providing altered timing signals from a second portion of memory in said ROM;
• means for synchronizing said timing signals and said altered timing signals from said ROM to said precision timed clock signal;
• switching means responsive to timing signals synchronized by said synchronizing means for converting said input signal into inphase and quadrature phase output signals, said switching means being responsive to altered timing signals synchronized by said synchronizing means for converting said input signal into phase-offset inphase and quadrature phase output signals which are shifted in phase by an amount corresponding to said predetermined phase offset;
• digital to analog (D/A) converter means for converting said inphase and quadrature phase output signals and said phase-offset inphase and quadrature phase output signals into digital inphase and quadrature phase output signals and digital phase-offset inphase and quadrature phase output signals;
• means for providing said digital inphase and quadrature phase output signals and said digital phase-offset inphase and quadrature phase output signals to a computing means;
• and
• means responsive to said digital inphase and quadrature phase output signals and said digital phase-offset inphase and quadrature phase output signals for computing a calibration correction for gain and orthogonality for signals provided by said switching means in response to said digital inphase and quadrature phase output signals and said digital phase-offset inphase and quadrature phase output signals,
• whereby said altered timing signals represent an effective shift in phase of said calibration reference signal when a phase offset signal is provided to said ROM.

A signal processing circuit responsive to an input signal having a predetermined frequency and a wide dynamic range for providing an inphase output signal and a quadrature phase output signal corresponding to said input signal, comprising:

• autoranging means for selecting one of a plurality of predetermined gain stages of amplification for said input signal and for providing a gain ranged output signal;
• a complex signal detection circuit for converting said gain ranged input signal into an inphase output signal and a quadrature phase output signal during a conversion cycle;
• and
• calibration signal means responsive to a calibration input signal provided during a calibration cycle for providing calibration correction signals to a utilization apparatus which utilizes said calibration correction signals to correct said inphase output signal and said quadrature phase output signal.

A commutating demodulator circuit responsive to an input signal at a predetermined frequency for providing an output signal referenced to the phase of a known phase reference signal during a conversion cycle, comprising:

• clock means for providing a clock signal having a frequency n times higher than said predetermined frequency of said input signal;
• locking means for phase locking said input signal and said clock signal;
• counter means for counting cycles of said clock signal modulo n and for providing count signals which subdivide a period of time corresponding to one cycle of said input signal;
• memory means responsive to said count signals for providing timing signals during said conversion cycle, said timing signals comprising a positive switching signal, a negative switching signal, a positive shunt signal, and a negative shunt signal,
• said positive switching signal and said negative switching signal being 180.degree. out of phase with respect to each other, and said positive shunt signal and said negative shunt signal being 180.degree. out of phase with respect to each other;
• first switching means responsive to said positive switching signal for switching said input signal to an integrating node;
• second switching means responsive to said negative switching signal for switching an inverted input signal to said integrating node;
• third switching means responsive to said positive shunt signal for holding the input voltage of said first switching means near ground during said negative switching signal;
• fourth switching means responsive to said negative shunt signal for holding the input voltage of said second switching means near ground during said positive switching signal;
• and
• synchronizing means for synchronizing said timing signals to said clock signal.