Integrated scalar and vector processors with vector addressing by the scalar processor
AssigneeErgo Computing, Inc.
InventorsGregory M. Papadopoulos, David E. Culler, James T. Pinkerton
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Abstract
A vector processor is closely integrated with a scalar processor. The scalar processor provides virtual-to-physical memory translation for both scalar and vector operations. In vector operations, a block move operation preformed by the scalar processor is intercepted, the write command in the operation is converted to a read, and data resulting from a vector operation is returned to the address specified by the block move write command. Writing of the data may be masked by a prior vector operation. Prefetch queues and write queues are provided between main memory and the vector processor. A microinstruction interface is supported for the vector processor.
Claims17
A data processing system comprising:
- a scalar microprocessor, coupled to the memory, which performs scalar operations, the scalar microprocessor comprising means for generating physical memory addresses, for addressing data in the memory, from virtual memory addresses, and
- a vector processor, coupled to the memory, responsive to vector instructions to receive a sequence of data from the memory which is addressed by a sequence of physical addresses form the scalar microprocessor for performing a vector operation on the received sequence of data and for storing a sequence of results of the vector operation in the memory at locations addressed by physical addresses from the scalar microprocessor;
- wherein:
- the scalar microprocessor responds to a block move instruction by reading data from locations in memory at a first set of addresses generated by the microprocessor and writing said data into locations in memory at a second set of addresses generated by the microprocessor, and
- in a vector operation, the vector processor receives a first sequence of data from locations in memory at the first set of addresses generated by the scalar microprocessor, inhibits writing of data into locations in memory at the second set of addresses generated by the scalar microprocessor, reads a second sequence of data which is different from the first sequence of data from locations at the second set of addresses, performs the vector operation on the first and second sequence of data and writes results of the vector operation in locations in memory at the second set of addresses.
In a data processing system a program responsive method of performing vector operations comprising:
- in a scalar microprocessor, generating physical memory addresses from virtual memory addresses for a vector operation by executing a block move instruction in which the scalar microprocessor attempts to read data from locations at a first set of addresses in memory and write the data from the first set of addresses into locations at a second set of addresses in memory;
- performing a vector operation in a vector processor on data from a memory which is addressed by physical addresses form the scalar microprocessor by receiving a first sequence of data from locations in memory at the first set of addresses generated by the scalar microprocessor, inhibiting writing of the data into locations in memory at the second set of addresses generated by the scalar microprocessor, reading a second sequence of data which is different from the first sequence of data from locations in memory at the second set of addresses, and performing the vector operation on the first and second sets of data;
- and
- storing results of the vector operation in the memory at the second set of addresses from the scalar microprocessor.
Dependencies are inferred from the claim text.