US 5,122,985 AGranted

Circuit and method for erasing EEPROM memory arrays to prevent over-erased cells

OwnerGiovani Santininventor

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Abstract

The device and process of this invention provide for elininating reading errors caused by over-erased cells by applying flash erasing pulses, then flash programming pulses to the cells of an EEPROM array. The flash erasing pulses are sufficient in strength to over-erase the cells. The flash programming pulses applied to the control gates have the same voltages as those used to program individual cells. The strength of the programming electric field pulses adjacent the floating gates is controlled by applying a biasing voltage to one of the source/drain regions of the cells. The biasing voltage controls the energy level of the programming field pulses such that only enough charge is transferred to the floating gates to cause the threshold voltages of the cells to have positive values less than that of a predetermined wordline select voltage.

Claims16

Dependent claims

A method for erasing a memory cell having at least one control terminal, a floating gate, a source terminal and a drain terminal, said memory cell programmable and erasable by applying electrical energy between said control terminal and at least one of said source and drain terminals to cause programming and erasing pulsed electric fields adjacent said floating gate, said memory cell readable using a preselected read voltage applied between said control terminal and at least one of said source terminal and said drain terminal, the method comprising:

initially applying an erasing electrical energy pulse having a first energy-level between said control terminal and said at least one of said source and drain terminals of said cell;
and
then applying a programing electrical energy pulse having a second energy-level between said control terminal and said at least one of said source and drain terminals of said cell;
wherein said first energy level of said erasing electrical energy pulse is sufficient to cause said cell to have a threshold voltage of opposite polarity to said preselected read voltage;
and
wherein said second energy level of said programming electrical energy pulse is such that said cell has a threshold voltage of the same polarity as said read voltage but that is less than said read voltage.

3 more elements

A non-volatile memory array, comprising:

memory cells arranged in rows and columns, each said memory cell having a source-drain path between first and second terminals and having a control-gate terminal;
a source-column line connected to each said first terminal of each said memory cell in a said column;
a drain-column line connected to each said second terminal of each said memory cell in a said column;
a wordline connected to each said control-gate terminal of each said memory cell in a said row;
each said memory cell having a floating-gate conductor insulated from said source-drain path and from said control gate, said floating-gate conductor being programmable and erasable by programming and erasing electrical energy pulses applied between said control gate and at least one of said first and said second terminals;
a column decoder connected to said source-column lines and said drain-column lines and a wordline decoder connected to said wordlines for providing said programming and erasing electrical energy pulses to said memory cells via said wordlines and at least one of said source-column lines and said drain-column lines;
and
an erase control circuit for causing said column decoder and said wordline decoder to provide said programming and erasing electrical energy pulses to said memory cells via said wordlines and at least one of said source-column lines and said drain-column lines, said control circuit causing said erasing electrical energy pulses having a sufficiently high energy-level to cause said floating gates initially to be over-erased, said control circuit subsequently causing said column decoder and said wordline decoder to provide said programming electrical energy pulses to said cells via said wordlines and at least one of said source-column lines and said drain-column lines.

5 more elements

A method of erasing a memory-cell array prior to programming said array, each said memory cell including a floating gate, the method comprising:

initially applying erasing electrical energy pulses to said cells of said memory cell array, said erasing electrical energy pulses having a energy-level sufficient to cause each memory cell of said array to have a negative threshold voltage;
then applying programming electrical energy pulses to said cells of said memory cell array, said programming electrical energy pulses having an energy-level sufficient to cause each cell of said array to have a positive threshold voltage.

Dependencies are inferred from the claim text.