Pulse width measurement technique

A system including a subject latch point having a clock input, a data input and a data output, said system further including a clock source point and clock distribution means for transmitting a clock signal from said clock source point to the clock input of said subject latch point, said system further including apparatus for measuring the width of clock pulses at the clock input of said subject latch point, said apparatus comprising:

• a test data source point;
• adjustable means for delivering strings of at least one clock pulse each to said clock source point, and for delivering to said test data source point a test data signal having a logic level transition at a presettable time relative to the time at which each of said strings of clock pulses are delivered to said clock source point;
• test data distribution means for transmitting test data signals from said test data source point to the data input of said subject latch point;
• means for adjusting said presettable time to determine a T1 setting at which the logic level transition in the test data signal delivered by said adjustable means in conjunction with each given string of clock pulses reaches the data input of said subject latch point at substantially the same time that the leading edge of the last clock pulse in said given string of clock pulses reaches the clock input of said subject latch point;
• and
• means for adjusting said presettable time to determine a T2 setting at which the logic level transition in the test data signal delivered by said adjustable means in conjunction with each particular string of clock pulses reaches the data input of said subject latch point at substantially the same time that the trailing edge of the last clock pulse in said particular string of clock pulses reaches the clock input of said subject latch point,
• the difference between said Tl and T2 settings being the width of the clock pulses at the clock input of said subject latch point.

A method for determining the width of clock pulses at the clock input of a subject latch point comprising the steps of:

• delivering to a clock source point a series of bursts of clock pulses having at least one clock pulse per burst;
• delivering a corresponding series of test data signals to a test data source point, each of said test data signals being delivered in response to a corresponding one of said bursts of clock pulses, each of said test data signals having a logic level transition at a presetable time relative to the time at which said corresponding one of said bursts of clock pulses are delivered to said clock source point;
• adjusting said presetable time for different ones of said bursts of clock pulses in said series to determine a T1 setting at which the logic level transition in the test data signal which corresponds to each given burst of clock pulses reaches a data input of said subject latch point at substantially the same time that the leading edge of the last clock pulse in said given burst of clock pulses reaches the clock input of said subject latch point;
• and
• adjusting said presetable time for different ones of said bursts of clock pulses in said series to determine a T2 setting at which the logic level transition in the test data signal which corresponds to each particular burst of clock pulses reaches a data input of said subject latch point at substantially the same time that the trailing edge of the last clock pulse in said particular burst of color pulses reaches the clock input of said subject latch point, the difference between said T1 and T2 settings being the width of the clock pulses at the clock input of said subject latch point.

A system including a plurality of latch points, said plurality of latch points including a subject latch point, each latch point in said plurality having a clock input, a data input and a data output, each latch point in said plurality supplying to its data output in response to a given clock pulse received at the clock input of said latch point a value responsive to that data present at the data input of said latch point when an effective edge of said given clock pulse reaches the clock input of said latch point, said system further including a clock source point and clock distribution means for transmitting a clock signal from said clock source point to the clock input of each of said plurality of latch points, said system further including apparatus for measuring the width of clock pulses at the clock input of said subject latch point, said apparatus comprising:

• a test data source point;
• adjustable means for delivering strings of at least one clock pulse each to said clock source point, and for delivering to said test data source point a test data signal having a logic level transition at a presettable time relative to the time at which each of said strings of clock pulses are delivered to said clock source point;
• test data distribution means for transmitting test data signals from said test data source point to the data input of said subject latch point;
• means for adjusting said presettable time to determine a T1 setting at which the logic level transition in the test data signal delivered by said adjustable means in conjunction with each given string of clock pulses reaches the data input of said subject latch point at substantially the same time that the leading edge of the last clock pulse in said given string of clock pulses reaches the clock input of said subject latch point;
• and
• means for adjusting said presettable time to determine a T2 setting at which the logic level transition in the test data signal delivered by said adjustable means in conjunction with each particular string of clock pulses reaches the data input of said subject latch point at substantially the same time that the trailing edge of the last clock pulse in said particular string of clock pulses reaches the clock input of said subject latch point,
• the difference between said T1 and T2 settings being the width of the clock pulses at the clock input of said subject latch point.