US 5,122,690 A · Interface circuits including driver circuits with switching noise reduction

Abstract

An interface circuit includes a generator for driving an interface signal to a receiver which produces an output signal in response thereto. The generator (or driver) includes a pair of relatively larger complementary conductivity field effect transistors and a pair of relatively smaller complementary conductivity field effect transistors (FETs), each pair in series circuit between the supply rails. The interface signal is produced at a connection of the center points of both pairs of FETs. A control device renders like ones of the FETs in each pair alternately conductive responsive to the input signal, however, the control device generates control signals for the FETs such that the relatively smaller FET of a given conductivity becomes conductive before the larger FET of that same conductivity. The receiver includes a voltage divider to attenuating and coupling the received interface signal to a high-gain amplifier which produces the output signal. Preferably, the signals have amplitudes sufficiently large to cause the interface circuit to operate as a digital interface. Further, it is preferred that two generators of opposite signal sense be employed to produce a differential interface signal, in which case the receiver includes a differential amplifier having opposite signal sense inputs to which the differential signals are applied through a differential voltage divider. In the preferred differential amplifier, opposite signal sense outputs are fed back in the regenerative sense to the two inputs to introduce hysteresis.

Claims22

Dependent claims

An interface circuit comprising:

driving means for producing at least one interface signal at a potential between that of first and second supply rails, said driving means including:
first and second field effect transistors coupled in series and respectively to said first and second supply rails, each of said first and second transistors having a given channel width,
third and fourth field effect transistors coupled in series and respectively to said first and second supply rails, said third and fourth transistors having given channel widths larger than those of said first and second transistors, respectively,
output means at which said interface signal is produced coupled to the series coupling of said first and second transistors and to the series coupling of said third and fourth transistors, and
control means coupled to said first, second, third and fourth transistors for alternately rendering said first and third transistors conductive and said second and fourth transistors conductive in response to an input signal, said control means further for rendering said first transistor conductive before rendering said third transistor conductive, and said second transistor conductive before rendering said fourth transistor conductive;
and
receiving means receiving said interface signal for producing an output signal at a potential between that of third and fourth supply rails in response to said input signal, said receiving means including:
potential dividing means coupled to said third and fourth supply rails and for receiving said interface signal, and having a node at which an attenuated signal directly responsive to said interface signal is produced, and
amplifying means coupled between said third and fourth supply rails and having an input connection coupled to said node for receiving said attenuated signal, for producing said output signal in response thereto.

6 more elements

A driving circuit for producing at least one interface signal at a potential between that of first and second supply rails, said driving circuit comprising:

first and second field effect transistors coupled in series and respectively to said first and second supply rails;
third and fourth field effect transistors coupled in series and respectively to said first and second supply rails, said third and fourth transistors having channel widths relatively larger than those of said first and second transistors;
output means at which said interface signal is produced coupled to the series coupling of said first and second transistors and to the series coupling of said third and fourth transistors;
and
control means coupled to said first, second, third and fourth transistors for applying first, second, third and fourth control signals to respective control electrodes of said first, second, third and fourth transistors for alternately rendering said first and third transistors conductive and said second and fourth transistors conductive in response to an input signal, said control means including means responsive to said fourth control signal for controlling said first control signal, and means responsive to said third control signal for controlling said second control signal, said control means further for rendering said first transistor conductive before rendering said third transistor conductive, and said second transistor conductive before rendering said fourth transistor conductive.

2 more elements

A receiving circuit for receiving an interface signal and producing an output signal at a potential between that of first and second supply rails in response to said interface signal, said receiving means comprising:

potential dividing means coupled to said first and second supply rails and for receiving said interface signal, said dividing means having a node at which an attenuated signal directly responsive to said interface signal is produced;
and
amplifying means coupled between said first and second supply rails and having an input means coupled to said node for receiving said attenuated signal, for producing said output signal in response thereto.

Dependencies are inferred from the claim text.

Interface circuits including driver circuits with switching noise reduction

Life of this patent

Interface circuits including driver circuits with switching noise reduction

Life of this patent

Abstract

Claims22