Current-injection logic (I.sup.2 L) driver for increasing fan-out

A circuit responsive to an input signal for providing a plurality of output signals, comprising:

• a first logic gate having an input at a common node and a plurality of outputs for providing a first portion of the plurality of output signals of the circuit;
• current supply means having an output for providing a current of predetermined magnitude to a first one of said plurality of outputs of said first logic gate;
• a first transistor having a base, an emitter and a collector, said base being coupled for receiving the input signal of the circuit, said collector being coupled to said common node, said emitter being coupled to a first power supply conductor;
• and
• a second transistor having a base, an emitter and a collector, said base being coupled to said output of said current supply means, said collector being coupled to a second power supply conductor, said emitter being coupled to said common node such that said plurality of outputs of said first logic gate each attempt to sink a current equal to said current of predetermined magnitude from said current supply means.

In a synchronous driver circuit responsive to an input signal for providing a plurality of output signals, comprising:

• a first logic gate having an input at a common node and a plurality of outputs for providing a first portion of the plurality of output signals of the circuit;
• current supply means having an output for providing a current of predetermined magnitude to a first one of said plurality of outputs of said first logic gate;
• a first transistor having a base, an emitter and a collector, said base being coupled for receiving the input signal, said collector being coupled to said common node, said emitter being coupled to a first power supply conductor;
• a second transistor having a base, an emitter and a collector, said base being coupled to said output of said current supply means, said collector being coupled to a second power supply conductor, said emitter being coupled to said common node such that said plurality of outputs of said first logic gate each attempt to sink a current equal to said current of predetermined magnitude from said current supply means;
• a third transistor having a base, an emitter and a collector, said base being coupled for receiving the input signal, said emitter being coupled to said first power supply conductor;
• and
• a fourth transistor having a base, an emitter and a collector, said emitter being coupled to said collector of said third transistor, said base and collector being coupled together to said base of said second transistor.