All-digital quadrature modulator

A digital quadrature modulator for generating a continuous-phase frequency-shift keyed (CPFSK) signal, said modulator comprising:

• means for translating serial input data having a predetermined bit rate into parallel input data;
• means for determining the phase quadrant of said serial input data in response to said bit rate and said parallel input data, thereby providing a phase control signal;
• means for interpolating between data bits of said serial input data, thereby providing an interpolation signal;
• and
• memory means for providing a digital representation of a CPFSK signal in response to said parallel input data, said phase control signal, and said interpolation signal.

A digital modulator for generating a quadrature modulated signal, said modulator comprising:

• first means for transforming a serial data signal into a parallel data signal including first memory means for storing data and providing a digital representation of in-phase (I) and quadrature-phase (Q) data signals in response to said serial data signal;
• means for providing a radio frequency (RF) carrier signal representative of an integer multiple of a bit clock signal;
• second means for transforming said radio frequency (RF) carrier signal into a digital carrier signal including second memory means for storing data and for providing a digital representation of in-phase (I) and quadrature-phase (Q) carrier signals in response to said digital carrier signal;
• means, including said second memory means, for digitally modulating said digital representation of I and Q carrier signals with said digital representation of I and Q data signals, thereby providing a digital representation of a quadrature modulated signal;
• and
• means for converting said digital representation of said quadrature modulated signal into an analog output signal having a precise modulation index, whereby digital-to-analog conversion is performed subsequent to quadrature modulation.

A means for generating an analog continuous-phase frequency-shift keyed (CPFSK) signal s(t) by quadrature modulating a radio frequency (RF) carrier f.sub.c with an input signal d(t) utilizing entirely digital circuitry, comprising:

• means for providing a data vector d of length L in response to d(t), wherein d has a bit rate 1/T;
• means for determining a phase parameter of d(t) in response to d , thereby providing a phase signal .theta.(t,d );
• means for providing an interpolation signal having a clock rate M/T;
• memory means for providing a digital output signal s(t,d ) when addressed with d and said interpolation signal, where
• s(t,d )=A cos [.omega..sub.c t+.theta.(t,d )],
• and where A=amplitude, and .omega..sub.c =2.pi.f.sub.c ;
• and
• means for converting s(t,d ) into s(t).

A digital quadrature modulator for generating a continuous-phase frequency-shift keyed (CPFSK) signal having a modulation index of 0.5 comprising:

• a formatting circuit comprising:
• an L-bit serial-to-parallel shift register into which a serial data signal is clocked at a bit rate 1/T, and which generates an L-bit parallel data signal representative of said serial data signal;
• a 2-bit up/down binary counter, clocked at the bit rate 1/T, having its up/down counter control determined by the most significant bit of said parallel data signal, thereby providing a 2-bit phase state signal;
• a log.sub.2 M-bit counter, clocked at M times the bit rate 1/T, which generates a log.sub.2 M-bit data interpolation signal representative of the binary state of said log.sub.2 M-bit counter;
• a memory circuit comprising:
• a memory device having B2.sup.(L+log.sbsp.2.sup.M+2) storage locations, having address lines coupled to said parallel data signal, said phase state signal, and said data interpolation signal, having a B-bit output, and having stored therein representations of CPFSK signal data with a modulation index of 0.5 at a carrier frequency of J/MT where J<M/2, and J and M are integers.

A method for generating a continuous-phase frequency-shift keyed (CPFSK) signal by quadrature modulating a radio frequency (RF) carrier with a digital input signal utilizing entirely digital techniques, said method comprising the steps of:

• translating serial input data having a predetermined bit rate into parallel input data;
• determining the phase quadrant of said serial input data in response to said bit rate and said parallel input data, thereby providing a phase control signal;
• interpolating between data bits of said serial input data, thereby providing an interpolation signal;
• addressing a memory utilizing said parallel input data, said phase control signal, and said interpolation signal;
• outputting a digital representation of a CPFSK signal from said memory;
• and converting said digital representation into an analog CPFSK output signal having a precise modulation index.

A method for generating a continuous-phase frequency-shift keyed (CPFSK) signal s(t) by a quadrature modulating a radio frequency (RF) carrier f.sub.c with a digital input signal d(t) utilizing entirely digital techniques, said method comprising the steps of:

• (a) providing a data vector d of length L in response to d(t), wherein d has a bit rate 1/T;
• (b) determining a phase parameter of d(t) in response to d , thereby providing a phase signal .theta.(t,d );
• (c) providing an interpolation signal having a clock rate M/T;
• (d) addressing a digital memory with d , .theta.(t,d ) and said interpolation signal;
• and
• (e) outputting s(t,d ) from said digital memory, wherein
• s(t,d )=A cos [.omega..sub.c t+.theta.(t,d )]
• and wherein A=amplitude and .omega..sub.c =2.pi.f.sub.c.

A method for modulating a radio frequency carrier f.sub.c with a digital input signal d(t), said method comprising the steps of:

• (a) providing a data vector d of length L in response to d(t), wherein d has a bit rate 1/T;
• (b) determining the phase quadrant of d(t) in response to d , thereby providing a phase signal .psi.(t,d );
• (c) providing an interpolation signal having a clock rate M/T;
• (d) calculating parameters s(t,d ) of s(t) according to the equation
• s(t,d )=A cos (.omega..sub.c t+.theta.(t,d )),
• where ##EQU14## and where A=amplitude, .omega..sub.c =2.pi.f.sub.c, h is the modulation index, and q(t) is the modulation phase pulse signal;
• (e) storing parameters s(t,d ) into a digital memory at address locations determined by d , .psi.(t,d ), and said interpolation signal;
• and
• (f) generating a modulated analog signal responsive to said stored parameters s(t,d ).

A method for quadrature modulation of a radio frequency (RF) carrier f.sub.c with an input signal d(t), said method comprising the steps of:

• (a) sampling the input signal d(t) at a sample rate 1/T, thereby creating a sampled data signal d(n) of length L;
• (b) defining parameters of a first signal I(t,d(n)) from said sampled data signal d(n);
• (c) defining parameters of a second signal Q(t,d(n)) from said sampled data signal d(n), wherein Q(t,d(n)) is in phase quadrature with I(t,d(n));
• calculating parameters of modulated signal Imod(t,d(n)) by multiplying I(t,d(n)) by cos(.sup..omega..sbsp.c (t)), where .sup..omega..sbsp.c =2.pi.f.sub.c ;
• (e) calculating parameters of modulated signal Qmod.sup.(t,d(n)) by multiplying Q(t,d(n)) by sin(.sup..omega..sbsp.c (t));
• (f) calculating parameters of a continuous-phase frequency shift keyed (CPFSK) signal s(t,d(n)) by subtracting Qmod.sup.(t,d(n)) from Imod .sup.(t,d(n)) ;
• (g) storing parameters of said CPFSK signal s(t,d(n)) into a digital memory;
• and
• (h) generating an analog signal responsive to said stored parameters of said CPFSK signal s(t,d(n)).

A radio transmitter comprising:

• means for providing a bit clock signal having a predetermined bit rate;
• means for providing serial input data having said bit rate;
• means for translating said serial input data into parallel input data;
• first memory means for storing data and for providing a digital representation of in-phase (I) and quadrature-phase (Q) component data signals in response to said parallel input data;
• means for providing a digital carrier signal representative of an integer multiple of said bit clock signal;
• second memory means for storing data and for providing a digital representation of in-phase (I) and quadrature-phase (Q) component carrier signals in response to said digital carrier signal;
• means, including said second memory means, for digitally modulating said I and Q carrier signals by said I and Q data signals, said second memory means further comprising means for storing data and for providing said digital quadrature modulating signal in response to said I and Q carrier signals and said I and Q data signals, thereby providing I and Q digital component signals;
• means, including said second memory means, for combining said I and Q digital component signals, thereby providing a digital quadrature modulated signal;
• means for converting said digital quadrature modulated signal into an analog output signal;
• and
• means for transmitting said analog output signal.