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US 5,121,010 AGranted
Phase detector with deadzone window
AssigneeMotorola, Inc.
InventorsGary W. Hoshizaki, Paul E. Fletcher, Laurin Ashby
Life of this patent
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AssigneeMotorola, Inc.
InventorsGary W. Hoshizaki, Paul E. Fletcher, Laurin Ashby
Estimating the term…
A phase lock loop for use in gate array applications with fixed transistors geometries maintains a predetermined phase delay between an input signal and an output signal. The phase comparison cycle operates over multiple periods of the input signal for increasing the operating frequency and simplifying timing considerations throughout the phase lock loop. A phase detector circuit detects a predetermined phase difference between the input signal and the output signal and provides a control signal and a clock signal at different transitions of the input signal. An up/down counter provides a count value migrating within a range of values in response to the control signal at the occurrence of the clock signal. The counter value selects a tap point of a delay line having single inverter resolution for delaying the input signal and maintaining the predetermined phase relationship between the input signal and the output signal of the phase lock loop. The updates to the delay line achieve steady state by waiting one or more periods of the input signal before the next phase comparison cycle preventing over-correction. The phase correction portion of the cycle is inhibited when the input signal and output signal are less than the predetermined phase difference thereby avoiding possible unnecessary corrections to the phase lock loop. The phase lock loop may be functionally divided among multiple macros in a gate array library and conveniently disposed in the gate array.
A phase detector circuit having first and second inputs respectively coupled for receiving first and second input signals and having first and second outputs for providing first and second output pulses, comprising:
In a phase lock loop of a gate array a phase detector circuit having first and second inputs respectively coupled for receiving first and second inputs signals and having a first output for providing a control signal and a second output for providing a clock signal, the phase detector comprising:
A method of detecting a predetermined phase difference between first and second input signal and providing first and second output pulses in response thereto, comprising the steps of:
A phase detector circuit having first and second inputs respectively coupled for receiving first and second inputs signals and having first and second outputs for providing first and second output pulses, comprising:
Dependencies are inferred from the claim text.