US 5,119,290 AGranted

Alias address support

AssigneeSun Microsystems, Inc.

InventorsWilliam V. Loo, John Watkins, Joseph Moran, William Shannon, Ray Cheng

Life of this patent

Estimating the term…

Loading patent…

Abstract

Improvements in workstations which utilizes virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes directed to the support of alias addresses, i.e., two or more virtual addresses which map to the same physical address in real memory Specifically, alias addresses are created so that their low order address bits are identical, modulo the size of the cache (as a minimum) for user programs which use alias addresses generated by the kernel, or wholely within the kernel. For alias addresses in the operating system, rather than user programs, which cannot be made to match in their low order address bits, their pages are assigned as "Don't Cache" pages in the memory management unit (MMU) employed by workstations which utilize virtual addressing.

Claims9

Dependent claims

In a computer system comprising at least one process being executed, an operating system allocating resources for said processes and utilizing alias addressing, a central processor (CPU) executing said processes and said operating system, a virtually addressed cache tag array (CTA) coupled to said CPU identifying virtual memory blocks being cached, a virtually addressed write back cache data array (CDA) coupled to said CPU caching said identified virtual memory blocks, a memory management unit (MMU) coupled to said CPU translating virtual addresses to physical addresses, a main memory (MM) coupled to said CPU storing virtual memory pages that are currently resident, a cache hit detector (CHD) coupled to said CPU and said CTA detecting cache hits, and processor control logic (PCL) coupled to said CPU, CTA, CDA, MMU, MM, and CHD controlling their operations, the improvement comprising:

a) when a first and second virtual addresses are alias to each other, but not members of a predetermined set of alias addresses, said operating system altering said first and second virtual addresses to equal each other in their n+m low order virtual address bits, thereby causing one cache location to be used for caching a first and second virtual memory locations,
said first and second virtual addresses comprising a first and second plurality ordered virtual address bits identifying a first and second virtual memory pages and said first and second virtual memory locations respectively, said first and second virtual memory locations being located within said first and second virtual memory pages,
said first and second virtual addresses being translated into the same physical address, said same physical address comprising a plurality of ordered physical address bits identifying a memory page and a memory location of said MM, said memory location being located within said memory page,
said predetermined set of alias addresses comprising a predetermined subset of virtual addresses of said operating system's address space, each of said predetermined subset of virtual addresses being alias to at least one other virtual address of said predetermined subset,
said CTA having n cache tag entries identifying n virtual memory blocks being cached, said CDA having n cache blocks of m cache locations caching said n identified virtual memory blocks, each of said n virtual memory blocks having m virtual memory locations;
b) when a virtual memory page comprising at least one virtual memory location identified by one of said predetermined set of virtual addresses, said MMU marking said virtual memory page as a Don't Cache Page , thereby, inhibiting virtual memory blocks of said marked virtual memory page from being cached, resulting in all data accesses to said marked virtual memory page being made directly to and from said MM by passing said CDA.

3 more elements

a) altering a first and second virtual addresses to equal each other in their n+m low order virtual address bits, when said first and second addresses are alias to each other, but not members of a predetermined set of alias addresses, thereby causing one cache location to be used for caching a first and second virtual memory locations,
said first and second virtual addresses comprising a first and second plurality ordered virtual address bits identifying a first and second virtual memory pages and said first and second virtual memory locations respectively, said first and second virtual memory locations being located within said first and second virtual memory pages,
said first and second virtual addresses being translated into the same physical address, said same physical address comprising a plurality of ordered physical address bits identifying a memory page and a memory location of said MM, said memory location being located within said memory page,
said predetermined set of alias addresses comprising a predetermined subset of virtual addresses of said operating system's address space, each of said predetermined subset of virtual addresses being alias to at least one other virtual address of said predetermined subset,
said CTA having n cache tag entries identifying n virtual memory blocks being cached, said CDA having n cache blocks of m cache locations caching said n identified virtual memory blocks, each of said n virtual memory blocks having m virtual memory locations;
b) marking a virtual memory page as a Don't Cache page, when said virtual memory pate comprising at least one virtual memory location identified by one of said predetermined set of virtual addresses, thereby, inhibiting virtual memory blocks of said marked virtual memory page from being cached, resulting in all data accesses to said marked virtual memory page being made directly to and from said MM by passing said CDA.

3 more elements

Dependencies are inferred from the claim text.