High performance interconnect system for an integrated circuit
AssigneeFairchild Camera and Instrument Corporation
InventorsMichael E. Thomas, Jeffrey D. Chinn
Life of this patent
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Abstract
A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.
Claims20
A semiconductor integrated circuit device including an interconnect structure for electrically connecting regions in a semiconductor substrate having contact areas disposed in a predetermined spaced relation, said interconnect structure comprising:
- a first level of interconnects disposed above said substrate and making electrical contact with at lease one of said contact areas;
- an array of posts, at least one post of said array of posts in electrical contact with said first level of interconnects and extending upwardly above said first level of interconnects;
- a metal layer disposed above said first level of interconnects, said metal layer making electrical contact with said at least one upwardly extending post;
- and,
- an air gap between said substrate and said metal layer.
A method of fabricating a semiconductor integrated circuit device including an interconnect structure for electrically connecting regions in a semiconductor substrate having contact areas disposed in a predetermined spaced relation, comprising the steps of:
- (a) patterning a first level of interconnects above said substrate in electrical contact with said contact areas;
- (b) forming an array of posts, at least one post of said array of posts in electrical contact with said first level of interconnects and extending upwardly above said first level of interconnects;
- (c) disposing a metal layer above said first level of interconnects in electrical contact with said at least one upwardly extending post;
- and,
- (d) forming an air gap between said substrate and said metal layer.
A semiconductor intergrated circuit device including an interconnect structure for electrically connecting regions in a semiconductor substrate having contact areas disposed in a predetermined spaced relation, said interconnect structure comprising:
- a first array of posts, a first post of said first array of posts being electrically coupled to at least one of said contact areas;
- a first level of interconnects disposed upon said first array of posts and making electrical contact with said first post;
- a second array of posts disposed upon said first level of interconnects above said first array of posts, a second post of said second array of posts making electrical contact with said first level of interconnects;
- a second level of interconnects disposed upon said second array of posts and making electrical contact with the posts of said second array of posts;
- and,
- an air gap between said first and second levels of interconnects.
A method of fabricating semiconductor intergrated integrated circuit device including an interconnect structure for electrically connecting regions in a semiconductor substrate having contact areas disposed in a predetermined spaced relation, comprising the steps of:
- (a) forming a first array of posts, a first post of said first array of posts being electrically coupled to at least one of said contact areas;
- (b) disposing a first level of interconnects upon said first array of posts in electrical contact with said first post;
- (c) forming a second array of posts upon said first level of interconnects above said first array of posts, a second post of said second array of posts making electrical contact with said first level of interconnects;
- (d) disposing a second level of interconnects upon said second array of posts in electrical contact with the posts of said second array of posts;
- and,
- (e) forming an air gap between said first and second levels of interconnects.
Dependencies are inferred from the claim text.