High speed digital to analog to digital communication system
AssigneeAdvanced Micro Devices, Inc.
InventorSalvatore Arcuri
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AssigneeAdvanced Micro Devices, Inc.
InventorSalvatore Arcuri
Estimating the term…
High speed communication of digital information is accomplished using an analog transmission format. A transmitter receiving digital data in parallel multi-bit words converts digital words in conversion clock cycles to a single analog signal relative to a DC level. The transmitter also includes a reference pulse generator which combines a reference pulse with the analog levels generated by the converter to form an analog output for transmission to the receiver. The receiver includes a detector receiving the analog output. In response to the reference pulse, the receiver generates a recovery clock. A flash analog-to-digital converter converts the analog levels in the analog output to multi-bit digital outputs. The parallel multi-bit words are regenerated in recovery clock cycles from sampling the multi-bit digital output once per cycle. Thus, by using a digital to analog to digital system, effective bit rates are achieved that are higher than the switching speeds of the transmitter and receiver.
An apparatus for communication of digital data across a communication link, comprising:
An apparatus for communication of digital data across a communication link, comprising:
An apparatus for communication of digital data across a communication link, comprising:
An apparatus for communication of digital data on a communication link, comprising:
An apparatus for communication of digital data on a communication link, the apparatus comprising:
An apparatus for communication of digital data across a communication link, the apparatus comprising:
An apparatus couplable to receive a first plurality of N-bit input streams of digital data from respective sources, each of the first plurality of N-bit input streams including a series of N-bit words, wherein the apparatus is couplable to an analog communication link, and the apparatus comprises:
An apparatus (FIG. 4) receiving a series of multibit data words and a conversion clock signal having cycles, wherein the apparatus comprises:
An apparatus (FIG. 6) receiving a series of multibit data words and a conversion clock signal having cycles, wherein the apparatus comprises:
An apparatus (FIG. 7) receiving a series of multibit data words and a conversion clock signal having cycles, wherein the apparatus comprises:
An apparatus (FIG. 5) receiving an analog input signal having analog reference pulses between pluralities of analog data pulses, wherein a data pulse has one of a predetermined number of values, and wherein the apparatus comprising:
Dependencies are inferred from the claim text.