Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device comprising the steps of:

• forming a first element region of a second conductivity type for a complementary MOS transistor and a second element region of the second conductivity type for a double-diffused MOS transistor on a semiconductor substrate of a first conductivity type so that the two regions are electrically isolated from each other;
• forming a first well diffusion layer of the first conductivity type and a second well diffusion layer of the second conductivity type in said first element region of the second conductivity type and a third well diffusion layer of the first conductivity type for compensation of the withstand voltage in said second element region of the second conductivity type;
• forming an undoped insulating layer on the entire surface of the resultant structure;
• patterning said insulating layer, and forming a first undoped gate electrode for a second channel type MOS transistor of said complementary MOS transistor over said second well diffusion layer, forming a second undoped gate electrode for a first channel type MOS transistor of said complementary MOS transistor over said first well diffusion layer, and forming a third undoped gate electrode for said double-diffused MOS transistor over said third well diffusion layer;
• forming a back gate region of the first conductivity type in said second element region, said back gate region being continuous to said third well diffusion layer and partly overlapped by said third gate electrode;
• introducing an impurity of the second conductivity type into said first well diffusion layer, said back gate region and said second element region forming source and drain regions of said second channel type MOS transistor, thereby forming source and drain regions of said double-diffused MOS transistor, said impurity being introduced into said first and third undoped gate electrodes at the same time;
• thermal-annealing for activating said impurity, thereby converting said first and third gate electrodes into first and third doped gate electrodes, respectively;
• and
• forming source and drain regions of a first channel type MOS transistor in said second well diffusion layer.