Method and apparatus for SRT division using gray coded quotient bit signals

Abstract

A method and apparatus for performing SRT division, in which Gray coded quotient bit signals are generated during each iteration from a divisor signal having Gray coded bits, and a dividend signal. Preferably, only the two most significant bits of the divisor signal are encoded into Gray code at the start of the division process, and the Gray coded quotient bit signals are decoded after each iteration, or after the final iteration, for use in generating the final quotient. In a preferred embodiment, the invention is a circuit capable of performing both single-precision and double-precision operations, and includes a pair of alternately operating divider block circuits each for generating a pair of quotient bits during each iteration cycle. The quotient bits emerging from each divider block circuit are decoded, and then shifted into one of two divider result registers depending upon their sign until 56 quotient bits (for double-precision operation) or 28 quotient bits (for single-precision operation) are accumulated in the divider result registers. When sufficient quotient bits have been accumulated, the invention asserts the contents of the divider result registers, a remainder sum register, and a remainder carry register, as output signals which may be combined to generate a final quotient signal.

Dependencies are inferred from the claim text.