Programmable digital filter

Programmable digital filter comprising:

• a) a plurality of parallel adders, each parallel adder having a first input, a second input and a parallel output, the parallel output of each said parallel adder being connected to said first input of the successive adder across a respective delay element, and a memory comprising:
• b) a memory bank including a plurality of addressable memory cells, wherein each memory cell holds a partial product of a preset coefficient and substantially all partial products held in said memory bank are non-redundant with other partial products held therein, said memory bank having an addressing input connected to a sampled digital signal to be filtered and a substantial number of outputs of said cells are connected to second inputs of at least two parallel adders, said memory bank comprising a number of bit lines not smaller than the total number of levels assumed by said sampled digital signal to be filtered, and a number of bits per line which is not smaller than the total number of bits of the partial products of present coefficients and given level of said sampled digital signal, said memory bank including a unit for decoding said sampled digital signal.