Semiconductor device having multilayered wiring structure with a small parasitic capacitance

A method of manufacturing semiconductor device comprising the steps of:

• forming a multilayered wirings using an organic substance as an interlayer insulating film;
• removing said organic substance;
• forming a compact insulating film covering the surface of said multilayered wirings;
• forming next an insulating film which is a mixture of a basic oxide and an acidic oxide between said multilayered wirings;
• subjecting said mixed insulating film to a heat treatment;
• and
• forming a porous insulating film by selectively removing said basic oxide or said acidic oxide.

A semiconductor device comprising a semiconductor substrate having semiconductor elements therein, an inorganic insulating layer covering said semiconductor substrate, at least one first contact hole selectively formed in said inorganic insulating layer to expose at least one part of said semiconductor substrate, first wiring layers selectively formed on said inorganic insulating layer, at least one of said wiring layers being in contact with said at least one part of said semiconductor substrate via said at least one first contact hole, a first porous insulating film formed on said inorganic insulating layer to intervene among said first wiring layers and formed on each of said first wiring layers to cover said first wiring layers, at least one second contact hole selectively formed in said first porous insulating film and said inorganic insulating layer to expose at least another part of said semiconductor substrate, a conductive layer filling said at least one second contact hole in contact with said other part of said semiconductor substrate, second wiring layers selectively formed on said first porous insulating film, at least one of said second wiring layers being in contact with said conductive layer, and a second porous insulating film formed on said first porous insulating film to intervene among said second wiring layers and formed on each of said second wiring layers to cover said second wiring layers, the volume of pores in each of said first and second porous insulating films being in the approximate range from 50% to 80% of the volume of each of said first and second porous insulating films, and each of said first and second porous insulating films having a dielectric constant which is not greater than 2.

A semiconductor device comprising a semiconductor substrate having semiconductor elements therein, an inorganic insulating layer covering said semiconductor substrate, at least one contact hole selectively formed in said inorganic insulating layer to expose at least one part of said semiconductor substrate, first wiring layers selectively formed on said inorganic insulating film, at least one of said first wiring layers being in contact with said at least one part of said semiconductor substrate via said at least one contact hole, a first pore-free insulating film formed on each of said first wiring layers, a first porous insulating film formed on said first pore-free insulating film to cover said first wiring layers and intervening among said first wiring layers, second wiring layers selectively formed on said first porous insulating film, a second pore-free insulating film intervening between said first porous insulating film and each of said second wiring layers, a third pore-free insulating film formed on each of said second wiring layers, and a second porous insulating film formed on said third pore-free insulating film to cover said second wiring layers and intervening among said second wiring layers, the volume of pores in each of said first and second porous insulating films being in the range from 50% to 80% of the volume of each of said first and second porous insulating films.