Semiconductor integrated circuit chip having an identification circuit therein

In a semiconductor integrated circuit chip having a pair of power supply terminals, at least three input terminals and an identification circuit means connected with one of said power supply terminals and with said three input terminals, the improvement wherein said identification circuit means comprises:

• voltage limiting means for limiting the potential difference between said one power supply terminal and one of said three input terminals to a predetermined limiting voltage level and for generating a predetermined control voltage by dividing the limiting voltage level;
• option means connected between the remaining two of said three input terminals for providing identification information indicative of said chip;
• and
• switch means connected in series to said option means, said switch means being controlled by said control voltage supplied from said voltage limiting means.

An integrated circuit chip comprising:

• internal circuit means;
• a pair of power supply terminals for supplying power to said internal circuit means;
• a plurality of input terminals for supplying signals to said internal circuit means;
• and
• identification circuit means, coupled between one of said power supply terminals and one of said input terminals, comprising:
• voltage limiting means for limiting a potential difference between said one power supply terminal and said one input terminal to a predetermined voltage level;
• and
• option means coupled to said voltage limiting means for optionally permitting current to flow therethrough;
• whereby said chip is identified according to whether said current flows through said identification circuit means.

An integrated circuit chip comprising:

• internal circuit means;
• a pair of power supply terminals for supplying power to said internal circuit means;
• at least three input terminals for supplying signals to said internal circuit means;
• and
• identification circuit means, coupled to one of said power supply terminals and at least three of said input terminals, comprising:
• voltage limiting means, coupled between said one power supply terminal and a first of said three input terminals, for limiting a potential difference between said one power supply terminal and said first input terminal to a predetermined voltage level and for generating a control voltage, said voltage limiting means comprising a plurality of MOS transistors connected in series with a resistor;
• a plurality of identification current paths coupled in parallel between a second and a third of said input terminals, each said path comprising a MOS transistor connected in series with a disconnectable member, said MOS transistor having a gate coupled to receive said control voltage generated by said voltage limiting means;
• whereby said chip is identifiable according to a sum of currents flowing through said plurality of identification current paths.