Pin electronics test circuit for IC device testing

A pin electronics card or unit (PEC) for applying test signals at a pin of an integrated circuit (IC) device under test (DUT) and for sensing pin signals received from a pin of the DUT, said PEC having motherboard coupling means for coupling to a motherboard of a test head of an IC device tester for receiving test control signals from the tester, and DUT board interconnect coupling means for coupling to a DUT board of the test head for driving and forcing test signals at a pin of a DUT mounted on the DUT board and for sensing and measuring pin signals received from a pin of a DUT mounted on the DUT board, said PEC comprising:

• test signal first electrical path means having a test connect and disconnect first node, said first electrical path means defining a test signal path between said first node and a first path coupling coupled to the DUT board interconnect coupling means for electrical connection to a pin of a DUT;
• first terminating means comprising a first terminating resistor and first terminating voltage source coupled in series to said first node providing substantially the function of a transmission line parallel termination for the first electrical path means for receiving pin signals from a pin of a DUT;
• first electronic switch means for electrically connecting and disconnecting the first terminating means with respect to said first node;
• AC test signal generating means coupled to said first node for generating and switching between AC test signals comprising data test signals of logic high and low potential levels and for driving said AC test signals on the first electrical path means for stimulating a pin of a DUT;
• second electronic switch means for electrically connecting and disconnecting the AC test signal generating means with respect to said first node;
• measuring means coupled to said test connect and disconnect first node for sensing and measuring pin signals from a pin of a DUT;
• test signal second electrical path means having a test connect and disconnect second node, said second electrical path means defining a test signal path between said second node and a second path coupling coupled to the DUT board interconnect coupling means for electrical connection to a pin of a DUT;
• second terminating means comprising a second terminating resistor and second terminating voltage source coupled in series to said second node providing substantially the function of a transmission line parallel termination for the second electrical path means for receiving pin signals from a pin of a DUT and for providing a bus mode termination;
• fifth electronic switch means for electrically connecting and disconnecting the second terminating means with respect to said second node;
• said measuring means being coupled to said test connect and disconnect second node for sensing and measuring pin signals from a pin of a DUT.

A pin electronics circuit for applying test signals at a pin of an integrated circuit (IC) device under test (DUT) and for sensing pin signals received from a pin of the DUT, said pin electronics circuit comprising:

• first and second test signal electrical path means having respective test connect and disconnect first and second nodes, said first and second electrical path means defining separate test signal paths between the respective first and second nodes and first and second path couplings for electrical connection to at least one pin of a DUT;
• first and second terminating means comprising respective first and second terminating resistors and respective first and second terminating voltage sources coupled in series to said first and second nodes providing substantially the function of transmission line parallel terminations for the respective first and second electrical path means for receiving pin signals from at least one pin of a DUT;
• first electronic switch means coupled for electrically connecting and disconnecting the first terminating means with respect to said first node;
• test signal generating means coupled to said first node for generating and electronically switching between test signals and for applying said test signals on the first electrical path means for stimulating a pin of a DUT;
• second electronic switch means coupled for electrically connecting and disconnecting the test signal generating means with respect to said first node;
• measuring means coupled to said test connect and disconnect first node for sensing and measuring pin signals from a pin of a DUT;
• third electronic switch means coupled for electrically connecting and disconnecting the second terminating means with respect to said second node.