Subranging ADC with error correction through increased fine step span and noise reducing layout

In a multiple-clock-cycle subranging type of analog-to-digital converter including a plurality of voltage comparators, a reference voltage ladder having a plurality of coarse steps and a plurality of fine steps within the coarse steps with a first group of the voltage comparators being connected to the plurality of coarse steps, a signal input for receiving unknown input voltages connected to the plurality of voltage comparators, and electronic switches connected to a second group of said voltage comparators and said reference voltage ladder, a method of converting an unknown input voltage to a multiple bit digital signal comprising the steps of:

• supplying a first unknown voltage to the signal input;
• sampling the first unknown voltage in the plurality of voltage comparators, autozeroing the first and second groups of voltage comparators with the sample, comparing the sample to each of the coarse steps of the voltage ladder in the first group of voltage comparators and providing a coarse output signal indicative of the particular coarse step of the reference voltage ladder which approximately matches the first unknown voltage;
• connecting the second group of voltage comparators, which includes twice as many plus one voltage comparators as the number of fine steps in a single coarse step, to the fine steps of the reference voltage ladder from a mid-point in the coarse step immediately below the particular coarse step, through the particular coarse step and to a mid-point in the coarse step immediately above the particular coarse step;
• comparing the sample to each of the connected fine steps of the voltage ladder in the second group of voltage comparators and providing a fine output signal indicative of the particular fine step of the reference voltage ladder which compares to the first unknown voltage;
• and
• utilizing the coarse output signal and the fine output signal to provide a multiple bit digital output signal.

In a multiple-clock-cycle subranging type of analog-to-digital converter including a plurality of voltage comparators, a reference voltage ladder having a plurality of coarse steps and a plurality of fine steps within the coarse steps with a first group of the voltage comparators being connected to the plurality of coarse steps, a signal input for receiving unknown input voltages connected to the plurality of voltage comparators, electronic switches connected to second and third groups of said voltage comparators and said reference voltage ladder, a method of converting an unknown input voltage into a multiple bit digital signal comprising the steps of:

• supplying a first unknown voltage to the signal input;
• sampling the first unknown voltage in the first group of voltage comparators and in the second group of voltage comparators, autozeroing the first and second groups of voltage comparators with the first sample, comparing the first sample to each of the coarse steps of the reference voltage ladder in the first group of voltage comparators and providing a coarse output signal indicative of the particular coarse step of the reference voltage ladder which approximately matches the first unknown voltage;
• activating electronic switches to connect the second group of voltage comparators to the fine steps of the reference voltage ladder from a mid-point in the coarse step immediately below the particular coarse step, through the particular coarse step and to a mid-point in the coarse step immediately above the particular coarse step;
• supplying a second unknown voltage to the signal input;
• sampling the second unknown voltage in the first and third groups of voltage comparators, and simultaneously autozeroing the first and third groups of voltage comparators with the second sample, comparing the first sample to each of the connected fine steps of the reference voltage ladder in the second group of voltage comparators and providing a fine output signal indicative of the particular fine step of the reference voltage ladder which compares to the first unknown voltage and simultaneously comparing the second sample to each of the coarse steps of the reference voltage ladder in the first group of voltage comparators and providing a second coarse output signal indicative of the second particular coarse step which approximately matches the second unknown voltage;
• activating electronic switches to disconnect the second group of voltage comparators from the reference voltage ladder and connect the third group of voltage comparators to the fine steps of the reference voltage ladder from a mid-point in the coarse step immediately below the second particular coarse step, through the second particular coarse step and to a mid-point in the coarse step immediately above the second particular coarse step;
• applying a third unknown voltage to the signal input;
• sampling the third unknown voltage in the first and second voltage comparators and simultaneously autozeroing the first and second groups of voltage comparators with the third sample, comparing the second sample to each of the connected fine steps of the voltage ladder in the third group of voltage comparators and providing a fine output signal indicative of the particular fine step of the reference voltage ladder which compares to the second unknown voltage and simultaneously comparing the third sample to each of the coarse steps of the reference voltage ladder in the first group of voltage comparators and providing a third coarse output signal indicative of the third particular coarse step which approximately matches the third unknown voltage;
• utilizing the coarse output signals and the fine output signals to provide a multiple bit digital output signal.

A multiple-clock-cycle subranging analog-to-digital converter including a plurality of voltage comparators, reference voltage ladder means having a plurality of coarse steps and a plurality of fine steps within the coarse steps, a first group of said voltage comparators being connected to the plurality of coarse steps, a signal input connected to said plurality of voltage comparators for receiving unknown input voltages, electronic switches connected to a second group of said voltage comparators and said reference ladder means, an MSB encoder connected to the first group of said voltage comparators and to said electronic switches, said MSB encoder receiving signals from the first group of said voltage comparators indicative of the approximate coarse step which coincides with an unknown voltage applied to said signal input and energizing said electronic switches to connect the second group of said voltage comparators to the fine steps of said reference voltage ladder means within and adjacent the indicated approximate coarse step, an LSB encoder connected to the second group of said voltage comparators, and an output buffer coupled to said MSB encoder and said LSB encoder for providing a multiple bit digital output signal which is indicative of the level of the unknown input voltage applied to said signal input, said reference voltage ladder means comprising:

• a plurality of resistors, at least one for each of the fine steps, connected into a fine resistance ladder, said resistors being positioned in a first common area on a semiconductor chip and the electronic switches being positioned in a second common area on the same chip so that connecting leads therebetween do not cross the fine resistance ladder, and said reference voltage ladder means further including a second plurality of resistors, at least one for each coarse step of said reference voltage ladder means, connected into a coarse resistance ladder electrically separate from said fine resistance ladder, with each of the first group of voltage comparators being connected to a different coarse step of the coarse resistance ladder, the first group of voltage comparators being positioned in a third common area on the same semiconductor chip, the third common area being on a different side of the first common area from the second common area so that leads connecting the first group of voltage comparators to the coarse resistance ladder do not cross either the first or the second resistance ladder.

In a multiple-clock-cycle subranging analog-to-digital converter integrated circuit including a plurality of voltage comparators, reference voltage ladder means having a plurality of coarse steps and a plurality of fine steps within the coarse steps with a first group of the voltage comparators being connected to the plurality of coarse steps and a second group of the voltage comparators being selectively connected to the reference voltage ladder means by a plurality of electronic switches, a method of forming the converter on a single semiconductor chip comprising the steps of:

• positioning the plurality of switches on the semiconductor chip in a first area;
• positioning a plurality of resistors, including at least one resistor for each fine step of the reference voltage ladder means, in a fine resistance ladder in a second area on the semiconductor chip so that leads connecting the plurality of switches to the fine resistance ladder do not cross the fine resistance ladder;
• forming the coarse steps with a separate plurality of coarse resistors connected into a coarse resistance ladder, electrically separate from the fine resistance ladder, in the second area on the semiconductor chip;
• and
• positioning the first group of voltage comparators on the semiconductor chip in a third area so that leads connecting the first group of voltage comparators to the coarse resistance ladder do not cross the coarse resistance ladder.