Buffer circuit for logic level conversion

A semiconductor interface circuit supplied with an input logic signal having either a first logic level or a second, different logic level, for producing an output logic signal in correspondence to the logic level of the input signal, comprising:

• a threshold circuit supplied with the input logic signal and an internal reference signal for discriminating the logic level thereof based upon a comparison of the logic level of the input logic signal and the internal reference signal and producing the output logic signal in response to the result of comparison;
• a reference circuit supplied with an external reference voltage for producing the internal reference signal;
• a first power supply terminal for receiving a first power voltage;
• and
• a second power supply terminal for receiving a second power voltage that is lower than the first power voltage;
• said threshold circuit comprising first load means having a first end connected to the first power supply terminal and a second end, a first enhancement mode field effect transistor having a drain connected to the second end of the first load means, a gate connected to the reference circuit for receiving the internal reference signal and a source, second load means having a first end connected to the source of the first enhancement mode field effect transistor and a second end connected to the second power supply terminal, and a first field effect transistor having a gate supplied with the input logic signal, a drain connected to the first power supply terminal and a source connected to the second power supply terminal, said threshold circuit producing the output logic signal at the drain of the enhancement mode field effect transistor;
• said reference circuit comprising third load means having a first end connected to the first power supply terminal and a second end, a second enhancement mode field effect transistor having a drain connected to the second end of the third load means, a gate connected to the drain of the second enhancement mode field effect transistor and further to the gate of the first enhancement mode field effect transistor and a source, said second enhancement mode field effect transistor producing the internal reference signal at the drain thereof, fourth load means having a first end connected to the source of the second enhancement mode field effect transistor and a second end connected to the second power supply terminal, and a second field effect transistor having a gate supplied with the external reference voltage, a drain connected to the first power supply terminal and a source connected to the second power supply terminal.