Programmable depth first-in, first-out memory

A first-in, first-out memory having a plurality of address locations for storing a programmable and reprogrammable number of data words, comprising:

• a read pointer for pointing to a read address in said memory;
• a depth pointer for pointing to a depth address in said memory, said depth address displaced from said read address by said number;
• a programmer coupled to said depth pointer for selectively programming and reprogramming said number into said depth pointer;
• a write pointer for pointing to a write address in said memory;
• and
• a write disabler coupled to said write pointer and said depth pointer and operable to disable the writing of data to said memory in response to the write address equalling the depth address.

A first-in, first out memory for storing a programmable number of data words at a plurality of address locations in said memory, comprising:

• a read pointer for pointing to a read address location in said memory from which a data word is to be read, said pointer incremented to a next read address location in response to receiving a read signal;
• a depth pointer for pointing to a depth address location in said memory displaced from said read address location by a programmed number of address locations, said depth pointer incremented to a next depth address location responsive to said read signal;
• a write pointer for pointing to a write address location related to the location to which data is to be written, said pointer incremented to a next write address location in response to a write signal;
• a programmer for selectively programming and reprogramming said programmed number into said read depth pointer;
• and
• a comparator for comparing the values of said write address location and said depth address location and operable to generate a memory capacity status flag responsive to the occurrence of a predetermined relation between said values.

A memory array having a plurality of addressable locations, comprising:

• a read address generator for pointing to a read address location from which a data word is to be read, said read address generator incrementing from a current read address location to a next read address location in response to a read signal;
• a write address generator for pointing to a write address location related to the location to which a data word is to be written, said write address generator incrementing from a current write address location to a next write address location in response to a write signal;
• a depth address generator for pointing to a depth address location in said array displaced from said read address location by a programmed number, said depth address generator incrementing from a current depth address location to a next depth address location in response to said read signal;
• a programmer for programming said depth generator such that the depth address will be a programmed number of addresses away from the read address;
• a first comparator for comparing said read address to said write address and operable to generate an empty signal in response to said read address and said write address being equal;
• a second comparator for comparing said depth address to said write address and operable to generate a full signal in response to said depth address and said write address being equal;
• and
• a controller for generating said read and write signals in response to external read and write signals, said controller disabled from generating read signals in response to receiving an empty signal and disabled from generating write signals in response to receiving a full signal.

A method for programming the depth of a first-in, first-out memory having a plurality of address locations, comprising the steps of:

• incrementing a read pointer from a current read address location in the memory to a next read address location in response to a read signal;
• programming a depth pointer to establish a depth address that is displaced from the read address by a programmed number of address locations;
• incrementing the depth pointer from a current depth address location in the memory to a next depth address location in the memory in response to the read signal;
• incrementing a write pointer from a current write address to a next write address in response to a write signal, the write address related to the write address location in the memory into which a data word is to be written;
• and
• disabling the writing of data to the memory in response to the write address equalling the depth address.