High speed dividing apparatus
AssigneeKabushiki Kaisha Toshiba
InventorMasafumi Takahashi
Life of this patent
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Abstract
An operation apparatus and method receive a dividend and a divisor as the input values of a divide operation processing, repeat a subtractive operation when the dividend and divisor are determined as being equal in sign to each other, and progress the repetition of an additive operation when the dividend and divisor are determined as being different in sign from each other. When the most significant bit of a quotient is calculated as having a negative number upon the sign equality of the dividend and divisor and when the most significant bit of the quotient is calculated as having a negative number upon the sign inequality of the dividend and divisor, an overflow is repeated at a time the other quotient bit conincides with the most significant bit of the quotient to detect it during a portion of the operation process.
Claims18
An operation apparatus including a divide operation device, comprising:
- dividend memory means for sequentially storing a dividend and a numerical value corresponding to an intermediate result of a divide operation;
- first sign bit storing means for storing a sign bit of the dividend;
- first shift means for shifting the numerical value in the dividend memory means to a 1-bit-higher bit position;
- divisor memory means for storing a divisor;
- second sign bit storing means for storing a sign bit of the divisor;
- second shift means for shifting the divisor in the divisor memory means to an upper bit position side by a difference between the number of bits of the divisor in the divisor memory means and that of the dividend;
- operation means for performing a subtractive operation between an output of the first shift means and an output of the second shift means when a value in the first sign bit storing means is equal to that in the second sign bit storing means and for performing an additive operation between an output of the first shift means and an output of the second shift means when an value in the first sign bit storing means is different from that in the second sign bit storing means;
- quotient determining means for determining, at least, whether or not a result of an operation by the operation means is "0", whether a carry or a borrow occurs, and a value of a quotient bit, on the basis of a value of the sign bit which is stored in the first sign bit storing means, said quotient determining means being connected to said first and second sign bit storing means, said first shift means and said operation means;
- select means for selecting a result of an operation by the operation means when a quotient bit which is determined by the quotient determining means is a first value and storing it in the dividend memory means and for selecting an output of the first shift means when a quotient bit which is determined by the quotient determining means is a second value and storing it in the dividend memory means;
- and
- control means for controlling said dividend and divisor memory means, first and second sign bit storing means, first and second shift means, operation means, quotient determining means and select means so that an operation by the operation means is performed a predetermined number of times.
An operation apparatus including a dividing device for performing a divide operation for finding a quotient between a dividend and a divisor, having a most significant bit as a sign bit, comprising:
- sign determining means for determining whether or not a dividend is equal in sign to a divisor;
- cycle determining means for determining, in said divide operation, a first cycle for finding the most significant bit of a quotient and a second cycle for finding other than the most significant bit of the quotient;
- bit determining means for determining whether or not the calculated quotient bit is a negative value;
- overflow determining means for determining the presence of an overflow in a divide operation when the sign determining means determines a sign equality of the dividend and divisor, when the cycle determining means is in the first cycle and when the bit determining means determines that the bit of the quotient represents a negative value, and for determining the presence of an overflow in the divide operation when the sign determining means determines a signal inequality of the dividend and divisor, when the cycle determining means is in the second cycle and when the bit determining means determines that the bit of the quotient represents a negative value and that the uppermost bit of the quotient already obtained is a negative value;
- and
- operation control means for controlling a progress of an operation processing, while supervising the sign, cycle, bit, and overflow determining means;
- wherein said sign determining means comprises an exclusive OR gate for determining whether or not said dividend nd divisor are equal in sign to each other, and
- said cycle determining means, said signal determining means and said bit determining means are each operatively connected to said overflow determining means, and said operation control means is connected to said sign, cycle, bit, and overflow determining means.
Dependencies are inferred from the claim text.