Method and apparatus for verifying timing during simulation of digital circuits

A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

• inputting a user specified timing template,
• simulating a logical function evaluation of said design for each successive simulation time instance,
• performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, and
• outputting the results of said time analysis for display to an end user.

A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

• inputting said digital circuit design to an analysis system,
• simulating a logical function evaluation of said design for each of successive simulation time instants,
• performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said inputs, said performing step comprising,
• determining a shortest and a longest delay path between said designated inputs and end points of said paths, and
• saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, and
• displaying the timing violation history of the saved paths to an end user.

A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

• inputting said digital circuit design to an analysis apparatus,
• inputting a user specified timing template to said apparatus,
• simulating a logical function evaluation of said design for each of successive simulation time instants,
• performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said inputs,
• setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, and
• displaying the timing violation history of paths as a result of said timing analysis of said digital circuit design.

A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

• inputting the digital circuit design to an analysis apparatus,
• simulating a logical function evaluation of said design for each of successive simulation time instants,
• performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths starting at said designated inputs,
• providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch, and
• displaying to an end user a timing violation history for said digital circuit design.

A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

• inputting said digital circuit design to an analysis apparatus,
• simulating a logical function evaluation of said design for each of successive simulation time instants,
• performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs,
• eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs,
• said performing step comprising
• determining a shortest and a longest delay path between said designated inputs and end points of said paths, and
• saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point,
• performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step,
• inputting a user specified timing template to said apparatus,
• setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested,
• providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch, and
• displaying to an end user a timing violation history for said digital circuit design.

Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

• means for inputting said digital circuit design to an analysis apparatus,
• means for simulating a logical function evaluation of said design for each of successive simulation time instants,
• means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, and
• means for eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs.

Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

• means for inputting said digital circuit design to an analysis apparatus,
• means for simulating a logical function evaluation of said design for each successive simulation time instance,
• means for performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, and
• means for outputting the results of said time analysis for display to an end user.

Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

• means for inputting said digital circuit design to the analysis apparatus,
• means for simulating a logical function evaluation of said design for each of successive simulation time instants,
• means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, said performing means comprising
• means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and
• means for saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, and
• means or displaying the timing violation history of the saved paths to an end user.

Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

• means for inputting said digital circuit design to said apparatus,
• means for inputting a user specified timing template,
• means for simulating a logical function evaluation of said design for each of successive simulation time instants,
• means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs,
• means for setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, and
• means for displaying the timing violation history of paths as a result of said timing analysis of said digital circuit design.

Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

• means for inputting the digital circuit design to said apparatus,
• means for simulating a logical function evaluation of said design for each of successive simulation time instants,
• means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths starting at said designated inputs,
• means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches, and
• means for displaying to an end user a timing violation history for said digital circuit design.

Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

• means for inputting said digital circuit design to an analysis apparatus,
• means for simulating a logical function evaluation of said design for each of successive simulation time instants,
• means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs,
• means for eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs,
• said performing means comprising
• means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and
• means for saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point,
• means for performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step,
• means for inputting a user specified timing template,
• means for setting the input stimuli with regard to at least one of said designated inputs n accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested,
• means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches, and
• means for displaying to an end user a timing violation history for said digital circuit design.