US 5,095,233 A · Digital delay line with inverter tap resolution

Abstract

A phase lock loop for use in gate array applications with fixed transistors geometries maintains a predetermined phase delay between an input signal and an output signal. The phase comparison cycle operates over multiple periods of the input signal for increasing the operating frequency and simplifying timing considerations throughout the phase lock loop. A phase detector circuit detects a predetermined phase difference between the input signal and the output signal and provides a control signal and a clock signal at different transitions of the input signal. An up/down counter provides a count value migrating within a range of values in response to the control signal at the occurrence of the clock signal. The counter value selects a tap point of a delay line having single inverter resolution for delaying the input signal and maintaining the predetermined phase relationship between the input signal and the output signal of the phase lock loop. The updates to the delay line achieve steady state by waiting one or more periods of the input signal before the next phase comparison cycle preventing over-correction. The phase correction portion of the cycle is inhibited when the input signal and output signal are less than the predetermined phase difference thereby avoiding possible unnecessary corrections to the phase lock loop. The phase lock loop may be functionally divided amony multiple macros in a gate array library and conveniently disposed in the gate array.

Claims19

Dependent claims

A circuit for delaying an input signal and providing an output signal, comprising:

first means having an input coupled for receiving the input signal and providing incremental delays of the input signal, said first means being responsive to a first control signal for selecting one of said incremental delays of the input signal at an output;
second means coupled to said output of said first means for generating first and second output signals from the delayed input signal, said first output signal operating substantially in-phase with the delayed input signal, said second output signal operating substantially of complementary phase with the delayed input signal;
third means coupled for inverting said second output signal of said second means and providing an inverted second output signal at an output;
and
fourth means responsive to a second control signal for alternately selecting between said first output signal of said second means and said inverted second output signal of said third means for providing the output signal of the circuit.

2 more elements

In a gate array a selectable delay circuit for providing an output signal delayed from an input signal, the selectable delay circuit comprising:

first means having an input coupled for receiving the input signal and having a plurality of outputs for providing incremental delays of the input signal;
second means having a plurality of inputs respectively coupled to said plurality of outputs of said first means and responsive to a first control signal for selecting one of said incremental delays of the input signal at an output;
third means coupled to said output of said second means for generating first and second output signals from said one of said incremental delays of the input signal, said first output signal operating substantially in-phase with said one of said incremental delays of the input signal, said second output signal operating substantially of complementary phase with said one of said incremental delays of the input signal;
fourth means coupled for inverting said second output signal of said third means and providing an inverted second output signal at an output;
and
fifth means responsive to a second control signal for alternately selecting between said first output signal of said third means and said inverted second output signal of said fourth means for providing the output signal of the circuit.

3 more elements

A circuit for delaying an input signal and providing an output signal, comprising:

first means for generating first and second output signals in response to the input signal, said first output signal operating substantially in-phase with the input signal, said second output signal operating substantially of complementary phase with the input signal;
second means having an input coupled for receiving said first output signal and providing incremental delays of said first output signal, said second means being responsive to a first control signal for selecting one of said incremental delays of said first output signal at an output;
third means coupled for inverting said second output signal and providing an inverted second output signal at an output;
fourth means having an input coupled for receiving said inverted second output signal and providing incremental delays of said inverted second output signal, said fourth means being responsive to said first control signal for selecting one of said incremental delays of said inverted second output signal at an output;
and
fifth means responsive to a second control signal for alternately selecting between said output of said second means and said output of said fourth means for providing the output signal of the circuit.

3 more elements

Dependencies are inferred from the claim text.

Digital delay line with inverter tap resolution

Life of this patent

Digital delay line with inverter tap resolution

Life of this patent

Abstract

Claims19