US 5,091,846 A · Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency

Abstract

A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation logic of the cache-memory management system. The cache-memory management system provides high speed virtual to real address translation along with associated system tag data defining access priorities and access modes associated with each respective address translation. The selectable access modes provides software definable features, such as cacheable data or non-cacheable data, write-through or copyback main memory update strategies for cacheable data, and real memory address space selection as main memory real address space, versus Boot ROM real address space versus input/output real address space. Page tables are loaded into main memory which contain address translation data and associated system tags. Upon initialization of the modifiable translation logic in the cache-memory management system, the address translations and associated system tags are loaded into the address translation logic of the cache-memory management system. Thereafter, as a part of the virtual to real address translation performed by the cache-memory management system, access modes and attributes are determined for each address translation, to provide for proper memory access of cacheable versus non-cacheable storage, etc., as part of the address translation and memory management function.

Claims20

Dependent claims

A computer system comprising:

a primary memory for storing pages of data;
a system bus coupled to the primary memory;
a first data processing element coupled to the system bus for processing data from the primary memory;
a second data processing element for processing data from the primary memory;
cache memory management means, coupled to said second data processing element and to said system bus, including:
a cache memory for storing data from said primary memory wherein data from the primary memory stored in the cache memory is accessed by the first and second data processing elements;
a cache controller for providing real address translation for virtual addresses received from the second data processing element, for selectively storing and retrieving data to and from said cache memory, and for communicating data between the cache memory and the second data processing element;
and
system tag means for storing a system tag which indicates one of a plurality of cache data storage modes;
wherein said cache controller includes:
cache mode effecting means for effecting the cache data storage mode indicated by said system tag;
and
data consistency means for ensuring shared data consistency between the first and second data processing elements, the data consistency means including system bus monitoring means, coupled to the system bus, for monitoring I/O requests over the system bus.

10 more elements

In a computing system having a primary memory for storing pages of data and a processor for processing said data, an integrated cache memory system comprising:

a cache a memory for storing data from said primary memory;
cache interface means for selectively coupling data between said processor and said cache memory;
primary memory interface means for coupling data between said primary memory and said cache memory;
translation means for providing an associative map of translations of virtual addresses to real addresses corresponding to data stored in said primary memory;
comparator means, coupled to said translation means, for providing a hit signal when a virtual address corresponds to data presently stored in said cache memory and for providing a miss signal when a virtual address does not correspond to data stored in said cache memory;
wherein said cache interface means selectively transfers data between said cache memory and said processor in response to a hit signal;
wherein said primary memory interface means selectively transfers data between said primary memory and said cache memory in response to a miss signal;
system tag means for storing a system tag which indicates one of a plurality of cache data storage modes, each cache data storage mode being provided for the variable for each page of data stored in said primary memory;
cache mode effecting means for effecting the cache data storage mode indicated by said system tag;
and
data consisting means for maintaining data consistency when said cache memory and said primary memory are independently accessed, the data consistency means including system bus monitoring means, coupled to the system bus, for monitoring I/O requests over the system bus.

8 more elements

A computer system comprising:

a processor;
a primary memory for storing pages of data;
a system bus coupled to the primary memory;
a boot loader memory coupled to said system bus for storing pages of data therein;
an input-output device for storing pages of data therein;
cache memory management means, coupled to the processor and to the system bus, including:
a cache memory for storing data from the primary memory;
a cache controller for selectively storing and retrieving data to and from the cache memory and for communicating data between the cache memory and the processor;
and
system tag means for storing a system tag which indicates one of a plurality of cache data storage modes and one of a plurality of address space attributes;
wherein said plurality of address space attributes include:
a boot memory address space attribute for indicating that a virtual address corresponds to a page of data stored in said boot memory;
an I/O address space attribute for indicating that a virtual address corresponds to a page of data stored in said input-output device;
a primary memory address space attribute for indicating that a virtual address corresponds to a page of data stored in said primary memory;
and
wherein the cache controller includes cache mode effecting means for effecting the cache data storage mode indicated by the system tag.

13 more elements

Dependencies are inferred from the claim text.

Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency

Life of this patent

Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency

Life of this patent

Abstract

Claims20