Configuration for testing and burn-in of integrated circuit chips

An integrated circuit chip package comprising:

• a substrate;
• a plurality of spacer blocks disposed on said substrate, said spacer blocks being spaced in a predetermined pattern which frames a multiplicity of distinct areas on said substrate's upper surface;
• a plurality of integrated circuit chips disposed on said substrate, each of said chips being disposed in one of the substrate areas framed by said spacer blocks such that the chip is bounded on each side by a spacer block, said chips each having interconnection pads thereon;
• at least one of said plurality of spacer blocks including a connection array for applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads, said connection array having a plurality of interconnection pads thereon;
• an encapsulant surrounding said integrated circuit chips and said spacer blocks, said encapsulant having an upper surface above the tops of the integrated circuit chips and the tops of the spacer blocks and having a plurality of via openings therein, said openings being aligned with at least some of said chip interconnection pads and said connection array interconnection pads;
• and
• a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between some of said openings and so as to provide electrical connection to at least between some of said chip interconnection pads and said connection array interconnection pads through said openings.

An integrated circuit chip package comprising:

• a substrate having an upper surface and a lower surface, said upper and lower substrate surfaces being substantially parallel;
• at least one integrated circuit chip disposed on the upper surface of said substrate, each integrated circuit chip having interconnection pads thereon;
• a solvent sensitive encapsulant surrounding said at least one integrated circuit chip, said encapsulant having an upper surface above the top of said at least one integrated circuit chip and having a plurality of via openings therein, said openings begin aligned with at least some of said chip interconnection pads;
• and
• a pattern of interconnection conductors disposed above the upper surface of said solvent sensitive encapsulant so as to extend through at least some of said openings and so as to provide electrical connection to a least some of said chip interconnection pads.