Self-aligned overlap MOSFET and method of fabrication
AssigneeIntel Corporation
InventorJulian J. B. Sanchez
Life of this patent
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Abstract
A high speed submicron transistor which exhibits a high immunity to hot electron degradation and is viable for VLSI manufacturing. An inner gate member is formed on a p type substrate. A first source region and a first drain region are disposed in the p type substrate in alignment with the inner gate member for forming a lightly doped region. A conductive spacer is formed adjacent to and is coupled to each side of the inner gate member on the gate oxide layer for forming a gate member which overlaps the lightly doped region. A second source region and a second drain region are disposed in the first source region and first drain regions, respectively, self-aligned with the outer edges of the conductive spacers to form source and drain contact areas.
Claims14
A high speed submicron channel hot electron resistant metal-oxide-semiconductor transistor ideal for VLSI circuits formed on a semiconductor substrate of a first conductivity type comprising:
- a gate oxide layer formed on said substrate;
- a polysilicon inner gate electrode of a predetermined length and width covering said gate oxide layer, said polysilicon inner gate electrode including laterally opposite sidewalls along said width of said inner gate electrode;
- a pair of lightly doped drain surface oxide layers disposed on respective areas of said substrate adjacent respective sidewalls of said polysilicon inner gate electrode;
- a first source region and a first drain region of a second conductivity type having a first concentration of second conductivity type dopant disposed in said substrate in alignment with said sidewalls of said polysilicon inner gate electrode for forming a pair of lightly doped spread apart regions;
- a pair of TiN spacers formed adjacent to and in electrical contact with respective sidewalls of said polysilicon inner gate electrode on respective lightly doped drain surface oxide layers for forming along with said polysilicon inner gate electrode a MOSFET gate electrode which overlaps said lightly doped regions;
- and
- a second source region and a second drain region of a second concentration dopant of said second conductivity type wherein said second concentration dopant is greater than said first concentration dopant, disposed in said first source region and said first drain region, respectively, self-aligned with the outer edges of said TiN spacers which provide masking.
A high speed submicron channel hot electron resistant metal-oxide-semiconductor transistor ideal for VLSI circuits formed on a semiconductor substrate of a first conductivity type comprising:
- a gate oxide layer formed on said substrate;
- a tungsten inner gate electrode of a predetermined length and width having a thickness of approximately 1000 .ANG. covering said gate oxide layer, said inner gate electrode including laterally opposite sidewalls along said width of said inner gate electrode;
- a pair of lightly doped drain surface oxide layers disposed on respective areas of said substrate adjacent respective sidewalls of said inner gate electrode;
- a first source region and a first drain region of a second conductivity type having a first concentration of second conductivity type dopant, said first source and drain regions disposed in said substrate in alignment with said sidewalls of said tungsten inner gate electrode for forming a pair of lightly doped spread apart regions;
- a pair of TiN spacers formed from a thin substantially planar TiN layer, said TiN spacers formed adjacent to and in electrical contact with respective sidewalls of said tungsten inner gate electrode on respective lightly doped drain surface oxide layers, said TiN spacers for forming along with said tungsten inner gate electrode a MOSFET gate electrode which overlaps said lightly doped regions;
- and
- a second source region and a second drain region of a second concentration dopant of said second conductivity type wherein said second concentration dopant is greater than said first concentration dopant, disposed in said first source region and said first drain region, respectively, self-aligned with the outer edges of said TiN spacers which provide masking.
A process for making a high speed submicron channel hot electron resistant metal-oxide-semiconductor transistor ideal for VLSI circuits on a semiconductor substrate of a first conductivity type comprising the steps of:
- forming a gate oxide layer on said substrate;
- forming a polysilicon inner gate electrode of a predetermined length and width on said gate oxide layer, said polysilicon inner gate electrode including laterally opposite sidewalls along said width of said inner gate electrode;
- implanting a first source region and a first drain region of a second conductivity type having a first concentration of second conductivity type dopant disposed in said substrate in alignment with said sidewalls of said polysilicon inner gate electrode for forming a pair of lightly doped spread apart regions;
- forming pair of TiN spacers adjacent to and in electrical contact with respective sidewalls of said polysilicon inner gate electrode on said gate oxide layer for forming along with said polysilicon inner gate electrode a MOSFET gate electrode which overlaps said lightly doped regions, said TiN spacers formed by depositing a substantially planar conformal layer of TiN on said gate oxide layer and on said polysilicon inner gate electrode with a low temperature process to prevent diffusion of said second conductivity type dopant from said first source and drain regions into said semiconductor substrate, said TiN spacers formed from said planar TiN layer by anisotropically dry etching said layer until end point detection;
- and
- implanting a second source region and a second drain region of a second concentration dopant of said second conductivity type wherein said second concentration dopant is greater than said first concentration dopant, in said first source region and said first drain region, respectively, self-aligned with the outer edges of said TiN spacers.
Dependencies are inferred from the claim text.